--- cortexr4regsgood.html 2016-09-07 22:43:48.287648131 +0200
+++ cortexr4regs.html 2016-09-20 08:20:12.584474185 +0200
@@ -2753,7 +2753,7 @@
Bits
Name Function
-
Value: 0 [31:5] Base address Defines bits [31:5] of the base address of a region.
+
Value: 33558528(0x2001000) [31:5] Base address Defines bits [31:5] of the base address of a region.
Value: 0 [4:0] - SBZ
To access an MPU Region Base Address Register, read or write CP15 with:
@@ -2813,7 +2813,7 @@
1 = address range is not part of this region.
- SBZ.
-
Value: 13(0xD) [5:1] Region size
+
Value: 0 [5:1] Region size
Defines the region size:
@@ -2937,7 +2937,7 @@
1 = no instruction fetches enabled.
Value: 0 [11] - Reserved.
-
Value: 3 [10:8] AP Access permission. Defines the data access permissions. For more information on AP bit values see, Table 4.36.
+
Value: 2 [10:8] AP Access permission. Defines the data access permissions. For more information on AP bit values see, Table 4.36.
Value: 0 [7:6] - SBZ.
Value: 1 [5:3] TEX Type extension. Defines the type extension attribute[a].
Value: 0 [2] S
@@ -3085,7 +3085,7 @@
Bits
Name Function
Value: 0 [31:4] - SBZ.
-
Value: 7 [3:0] Region Defines the group of registers to be accessed. Read the MPUIR to determine the number of supported regions, see c0, MPU Type Register.
+
Value: 0 [3:0] Region Defines the group of registers to be accessed. Read the MPUIR to determine the number of supported regions, see c0, MPU Type Register.
To access the RGNR, read or write CP15 with: