Table 4.3. MIDR Register bit assignments

Bits

Name Function

Value: 65(0x41) [31:24] Implementer

Indicates implementer:

0x41 = ARM Limited.

Value: 1 [23:20] Variant

Identifies the major revision of the processor. This is the major revision number n in the rn part of the rnpn description of the product revision status.

Value: 7 [19:16] Architecture

Indicates the architecture version:

0xF = see feature registers.

Value: 1044(0x414) [15:4] Primary part number

Indicates processor part number:

0xC14 = Cortex-R4.

Value: 4 [3:0] Revision

Identifies the minor revision of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status.

Note

If an MRC instruction is executed with CRn = c0, Opcode_1 = 0, CRm = c0, and an Opcode_2 value corresponding to an unimplemented or reserved ID register, the system control coprocessor returns the value of the MIDR.

To access the MIDR Register, read CP15 with:

MRC p15, 0, , c0, c0, 0 ; Read MIDR

----------------------------------

Table 4.4. CTR Register bit assignments

Bits

Name

Function

Value: 0 [31:28]

- Always b1000.

Value: 0 [27:24] CWG

Cache Write-back Granule:

0x0 = no information provided. See maximum cache line size in c0, Current Cache Size Identification Register.

Value: 0 [23:20] ERG

Exclusives Reservation Granule:

0x0 = no information provided.

Value: 3 [19:16] DMinLine

Indicates log2 of the number of words in the smallest cache line of the data and unified caches controlled by the processor:

0x3 = eight words in an L1 data cache line.

Value: 1 [15:14] -

Always 0x3.

Value: 0 [13: 4] - Always 0x000.

Value: 3 [3: 0] IMinLine

Indicates log2 of the number of words in the smallest cache line of the instruction caches controlled by the processor:

0x3 = eight words in an L1 instruction cache line.

To access the CTR, read CP15 with:

MRC p15, 0, , c0, c0, 1 ; Read CTR

------------------------------

Table 4.5. TCMTR Register bit assignments

Bits

Name Function

Value: 0 [31:29] - Always 0, indicating v6 format TCMTR.

Value: 0 [28:19] - SBZ.

Value: 1 [18:16] BTCM Specifies the number of BTCMs implemented. This is always set to b001 because the processor has one BTCM.

Value: 0 [15:3] - SBZ.

Value: 1 [2:0] ATCM Specifies the number of ATCMs implemented. Always set to b001. The processor has one ATCM.

To access the TCMTR, read CP15 with:

MRC p15, 0, , c0, c0, 2 ; Returns TCMTR

----------------------------------

Table 4.6. MPUIR Register bit assignments

Bits Name Function

Value: 0 [31:16] - SBZ.

Value: 12(0xC) [15:8] DRegion Specifies the number of unified MPU regions. Set to 0, 8 or 12 data MPU regions.

Value: 0 [7:1] - SBZ.

Value: 0 [0] S

Specifies the type of MPU regions, unified or separate, in the processor.

Always set to 0, the processor has unified memory regions.

To access the MPUIR, read CP15 with:

MRC p15, 0, , c0, c0, 4 ; Returns MPU information

-----------------------------------

4.3.6. c0, Multiprocessor ID Register

The MPIDR characteristics are:

Purpose

Enables CPUs to be recognized and characterized within a multi-processor system.

Usage constraints

The MPIDR is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Because this is a uniprocessor system, this register is Read-As-Zero.

To access the MPIDR, read CP15 with:

MRC p15, 0, , c0, c0, 5 ; Returns Multiprocessor ID information

--------------------------------

c0, Processor Feature Register 0

The PFR0 characteristics are:

Purpose

Provides information about the execution state support and programmers model for the processor.

Usage constraints

PFR0 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.7.

Figure 4.11 shows the PFR0 bit assignments.

Figure 4.11. PFR0 Register bit assignments

Table 4.7 shows the PFR0 bit assignments.

Table 4.7. PFR0 Register bit assignments

Bits Name Function

Value: 0 [31:16] -

SBZ.

Value: 0 [15:12] State3

Indicates support for Thumb Execution Environment (ThumbEE):

0x0 = no support.

Value: 1 [11:8] State2

Indicates support for acceleration of execution environments in hardware or software:

0x1 = the processor supports acceleration of execution environments in software.

Value: 3 [7:4] State1

Indicates type of Thumb encoding that the processor supports:

0x3 = the processor supports Thumb encoding with all Thumb instructions.

Value: 1 [3:0] State0

Indicates support for ARM instruction set:

0x1 = the processor supports ARM instructions.

To access the PFR0 read CP15 with:

MRC p15, 0, , c0, c1, 0 ; Read PFR0

c0, Processor Feature Register 1

The PFR1 characteristics are:

Purpose

Provides information about the execution state support and programmers model for the processor.

Usage constraints

PFR1 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.8.

Figure 4.12 shows the PFR1 bit assignments.

Figure 4.12. PFR1 Register bit assignments

Table 4.8 shows the PFR1 bit assignments.Register

Table 4.8. PFR1 bit assignments

Bits

Name Function

Value: 0 [31:12] -

SBZ.

Value: 0 [11:8] Microcontroller programmers model

Indicates support for Microcontroller programmers model:

0x0 = no support.

Value: 0 [7:4] Security extension

Indicates support for Security Extensions architecture:

0x0 = no support.

Value: 1 [3:0] ARMv4 Programmers model

Indicates support for standard ARMv4 programmers model:

0x1 = the processor supports the ARMv4 model.

To access the PFR1 read CP15 with:

MRC p15, 0, , c0, c1, 1 ; Read PFR1

------------------------------------

4.3.7. The Processor Feature Registers

The processor has two Processor Feature Registers, PFR0 and PFR1. This section describes:

c0, Processor Feature Register 0

c0, Processor Feature Register 1.

c0, Processor Feature Register 0

The PFR0 characteristics are:

Purpose

Provides information about the execution state support and programmers model for the processor.

Usage constraints

PFR0 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.7.

Figure 4.11 shows the PFR0 bit assignments.

Figure 4.11. PFR0 Register bit assignments

Table 4.7 shows the PFR0 bit assignments.

Table 4.7. PFR0 Register bit assignments

Bits Name Function

Value: 1 [31:16] -

SBZ.

Value: 0 [15:12] State3

Indicates support for Thumb Execution Environment (ThumbEE):

0x0 = no support.

Value: 4 [11:8] State2

Indicates support for acceleration of execution environments in hardware or software:

0x1 = the processor supports acceleration of execution environments in software.

Value: 0 [7:4] State1

Indicates type of Thumb encoding that the processor supports:

0x3 = the processor supports Thumb encoding with all Thumb instructions.

Value: 0 [3:0] State0

Indicates support for ARM instruction set:

0x1 = the processor supports ARM instructions.

To access the PFR0 read CP15 with:

MRC p15, 0, , c0, c1, 0 ; Read PFR0

-----------------------------------

c0, Processor Feature Register 1

The PFR1 characteristics are:

Purpose

Provides information about the execution state support and programmers model for the processor.

Usage constraints

PFR1 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.8.

Figure 4.12 shows the PFR1 bit assignments.

Figure 4.12. PFR1 Register bit assignments

Table 4.8 shows the PFR1 bit assignments.Register

Table 4.8. PFR1 bit assignments

Bits

Name Function

Value: 0 [31:12] -

SBZ.

Value: 0 [11:8] Microcontroller programmers model

Indicates support for Microcontroller programmers model:

0x0 = no support.

Value: 0 [7:4] Security extension

Indicates support for Security Extensions architecture:

0x0 = no support.

Value: 1 [3:0] ARMv4 Programmers model

Indicates support for standard ARMv4 programmers model:

0x1 = the processor supports the ARMv4 model.

To access the PFR1 read CP15 with:

MRC p15, 0, , c0, c1, 1 ; Read PFR1

---------------------------------

4.3.8. c0, Debug Feature Register 0

The ID_DFR0 characteristics are:

Purpose

Provides information about the debug system for the processor.

Usage constraints

ID_DFR0 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.9.

Figure 4.13 shows the ID_DFR0 bit assignments.

Figure 4.13. ID_DFR0 Register bit assignments

Table 4.9 shows the ID_DFR0 bit assignments.

Table 4.9. ID_DFR0 Register bit assignments

Bits

Name Function

Value: 0 [31:24] -

SBZ.

Value: 0 [23:20]

Microcontroller Debug model - memory mapped

Indicates support for the microcontroller debug model - memory mapped:

0x0 = no support.

Value: 1 [19:16] Trace debug model - memory mapped

Indicates support for the trace debug model - memory mapped:

0x1 = trace supported, memory mapped access.

Value: 0 [15:12] Trace debug model - coprocessor

Indicates support for the trace debug model - coprocessor:

0x0 = no support.

Value: 4 [11:8] Core debug model - memory mapped

Indicates the type of embedded processor debug model that the processor supports:

0x4 = ARMv7 based model - memory mapped.

Value: 0 [7:4] Secure debug model

Indicates the type of secure debug model that the processor supports:

0x0 = no support.

Value: 0 [3:0] Core debug model - coprocessor

Indicates the type of applications processor debug model that the processor supports:

0x0 = no support.

To access the ID_DFR0 read CP15 with:

MRC p15, 0, , c0, c1, 2 ; Read ID_DFR0

-----------------------------------

4.3.9. c0, Auxiliary Feature Register 0

The ID_AFR0 characteristics are:

Purpose

Provides additional information about the features of the processor.

Usage constraints

The ID_AFR0 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

In this processor, the ID_AFR0 reads as 0x00000000.

To access the ID_AFR0 read CP15 with:

MRC p15, 0, , c0, c1, 3 ; Read ID_AFR0.

------------------------------

c0, Memory Model Feature Register 0

The ID_MMFR0 characteristics are:

Purpose

The ID_MMFR0 provides information about the memory model, memory management, and cache support operations of the processor.

Usage constraints

The ID_MMFR0 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.10.

Figure 4.14 shows the ID_MMFR0 bit assignments.

Figure 4.14. ID_MMFR0 Register bit assignments

Table 4.10 shows the ID_MMFR0 bit assignments.

Table 4.10. ID_MMFR0 Register bit assignments

Bits Name Function

Value: 0 [31:28] Innermost shareability

Indicates the innermost shareability domain implemented.

RAZ/UNK because only one shareability domain is implemented, see bits [15:12].

Value: 0 [27:24] FCSE

Indicates support for Fast Context Switch Extension (FCSE):

0x0 = no support.

Value: 2 [23:20] Auxiliary Registers

Indicates support for the auxiliary registers:

0x2 = the processor supports the Auxiliary Instruction and Data Fault Status Registers (AIFSR and ADFSR) and the ACTLR.

Value: 1 [19:16] TCM support

Indicates support for TCM and associated DMA:

0x1 = implementation defined.

Value: 0 [15:12] Shareability levels

Indicates the number of shareability levels implemented:

0x0 = one level of shareability implemented.

Value: 0 [11:8] Outermost shareability

Indicates the outermost shareability domain implemented:

0x0 = implemented as non-cacheable.

Value: 3 [7:4] PMSA

Indicates support for Physical Memory System Architecture (PMSA):

0x3 = the processor supports PMSAv7 (subsection support).

Value: 0 [3:0] VMSA

Indicates support for Virtual Memory System Architecture (VMSA):

0x0 = no support.

To access the ID_MMFR0 read CP15 with:

MRC p15, 0, , c0, c1, 4 ; Read ID_MMFR0.

--------------------------------------

c0, Memory Model Feature Register 1

The ID_MMFR1 Register characteristics are:

Purpose

Provides information about the memory model, memory management, and cache support of the processor.

Usage constraints

The ID_MMFR1 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.11.

Figure 4.15 shows the ID_MMFR1 bit assignments.

Figure 4.15. ID_MMFR1 Register bit assignments

Table 4.11 shows the ID_MMFR1 bit assignments.

Table 4.11. ID_MMFR1 Register bit assignments

Bits

Name Function

Value: 0 [31:28] Branch predictor

Indicates Branch Predictor management requirements:

0x0 = no MMU present.

Value: 0 [27:24] L1 test clean operations

Indicates support for test and clean operations on data cache, Harvard or unified architecture:

0x0 = no support.

Value: 0 [23:20] L1 cache maintenance operations (unified)

Indicates support for L1 cache, entire cache maintenance operations, unified architecture:

0x0 = no support.

Value: 0 [19:16] L1 cache maintenance operations (Harvard)

Indicates support for L1 cache, entire cache maintenance operations, Harvard architecture:

0x0 = no support.

Value: 0 [15:12] L1 cache line maintenance operations - Set and Way (unified)

Indicates support for L1 cache line maintenance operations by Set and Way, unified architecture:

0x0 = no support.

Value: 0 [11:8] L1 cache line maintenance operations - Set and Way (Harvard)

Indicates support for L1 cache line maintenance operations by Set and Way, Harvard architecture.

0x0 = no support.

Value: 0 [7:4] L1 cache line maintenance operations - MVA (unified)

Indicates support for L1 cache line maintenance operations by address, unified architecture.

0x0 = no support.

Value: 0 [3:0] L1 cache line maintenance operations - MVA (Harvard)

Indicates support for L1 cache line maintenance operations by address, Harvard architecture.

0x0 = no support.

To access the ID_MMFR1 read CP15 with:

MRC p15, 0, , c0, c1, 5 ; Read ID_MMFR1.

------------------------------------

c0, Memory Model Feature Register 2

The ID_MMFR2 characteristics are:

Purpose

The ID_MMFR2 provides information about the memory model, memory management, and cache support operations of the processor.

Usage constraints

The ID_MMFR2 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.12.

Figure 4.16 shows the ID_MMFR2 bit assignments.

Figure 4.16. ID_MMFR2 Register bit assignments

Table 4.12 shows the ID_MMFR2 bit assignments.

Table 4.12. ID_MMFR2 bit assignments

Bits

Name Function

Value: 0 [31:28] Hardware access flag

Indicates support for Hardware Access Flag:

0x0 = no support.

Value: 1 [27:24] WFI

Indicates support for Wait-For-Interrupt stalling:

0x1 = the processor supports Wait-For-Interrupt.

Value: 2 [23:20] Memory barrier

Indicates support for memory barrier operations:

0x2 = the processor supports:

DSB (formerly DWB)

ISB (formerly Prefetch Flush)

DMB.

Value: 0 [19:16] TLB maintenance operations (unified)

Indicates support for TLB maintenance operations, unified architecture:

0x0 = no support.

Value: 0 [15:12] TLB maintenance operations (Harvard)

Indicates support for TLB maintenance operations, Harvard architecture:

0x0 = no support.

Value: 0 [11:8] L1 cache maintenance range operations (Harvard)

Indicates support for cache maintenance range operations, Harvard architecture:

0x0 = no support.

Value: 0 [7:4] L1 background prefetch cache operations

Indicates support for background prefetch cache range operations, Harvard architecture:

0x0 = no support.

Value: 0 [3:0] L1 foreground prefetch cache operations

Indicates support for foreground prefetch cache range operations, Harvard architecture:

0x0 = no support.

To access the ID_MMFR2 read CP15 with:

MRC p15, 0, , c0, c1, 6 ; Read ID_MMFR2.

-----------------------------------

c0, Memory Model Feature Register 3

The ID_MMFR3 characteristics are:

Purpose

Provides information about the two cache line maintenance operations for the processor.

Usage constraints

The ID_MMFR3 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.13.

Figure 4.17 shows the ID_MMFR3 bit assignments.

Figure 4.17. ID_MMFR3 bit assignments

Table 4.13 shows the ID_MMFR3 bit assignments.

Table 4.13. ID_MMFR3 Register bit assignments

Bits

Name

Function

Value: 0 [31:28] Supersection support RAZ because this is a PMSA implementation.

Value: 0 [27:24] - SBZ

Value: 0 [23:20] Coherent walk RAZ because this is a PMSA implementation.

Value: 0 [19:16] - SBZ

Value: 0 [15:12] Maintenance broadcast

Indicates whether cache maintenance operations are broadcast:

0x0 = cache maintenance operations only affect local structures.

Value: 2 [11:8] Branch predictor maintenance operations

Indicates support for branch predictor maintenance operations in systems with hierarchical cache maintenance operations:

0x2 = supports invalidate entire branch predictor array and invalidate branch predictor by MVA[a].

Value: 1 [7:4] Hierarchical cache maintenance operations by Set and Way

Indicates support for hierarchical cache maintenance operations by Set and Way:

0x1 = the processor supports invalidate cache, clean and invalidate, and clean by Set and Way.

Value: 1 [3:0] Hierarchical cache maintenance operations by MVA

Indicates support for hierarchical cache maintenance operations by address:

0x1 = the processor supports:

Invalidate data cache by address

Clean data cache by address

Clean and invalidate data cache by address

Invalidate instruction cache by address

Invalidate all instruction cache entries.

[a] Both of these operations are NOP on Cortex-R4.

To access the ID_MMFR3 read CP15 with:

MRC p15, 0, , c0, c1, 7 ; Read ID_MMFR3.

-------------------------------------------

c0, Memory Model Feature Register 1

The ID_MMFR1 Register characteristics are:

Purpose

Provides information about the memory model, memory management, and cache support of the processor.

Usage constraints

The ID_MMFR1 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.11.

Figure 4.15 shows the ID_MMFR1 bit assignments.

Figure 4.15. ID_MMFR1 Register bit assignments

Table 4.11 shows the ID_MMFR1 bit assignments.

Table 4.11. ID_MMFR1 Register bit assignments

Bits

Name Function

Value: 0 [31:28] Branch predictor

Indicates Branch Predictor management requirements:

0x0 = no MMU present.

Value: 1 [27:24] L1 test clean operations

Indicates support for test and clean operations on data cache, Harvard or unified architecture:

0x0 = no support.

Value: 1 [23:20] L1 cache maintenance operations (unified)

Indicates support for L1 cache, entire cache maintenance operations, unified architecture:

0x0 = no support.

Value: 0 [19:16] L1 cache maintenance operations (Harvard)

Indicates support for L1 cache, entire cache maintenance operations, Harvard architecture:

0x0 = no support.

Value: 1 [15:12] L1 cache line maintenance operations - Set and Way (unified)

Indicates support for L1 cache line maintenance operations by Set and Way, unified architecture:

0x0 = no support.

Value: 1 [11:8] L1 cache line maintenance operations - Set and Way (Harvard)

Indicates support for L1 cache line maintenance operations by Set and Way, Harvard architecture.

0x0 = no support.

Value: 1 [7:4] L1 cache line maintenance operations - MVA (unified)

Indicates support for L1 cache line maintenance operations by address, unified architecture.

0x0 = no support.

Value: 1 [3:0] L1 cache line maintenance operations - MVA (Harvard)

Indicates support for L1 cache line maintenance operations by address, Harvard architecture.

0x0 = no support.

To access the ID_MMFR1 read CP15 with:

MRC p15, 0, , c0, c1, 5 ; Read ID_MMFR1.

c0, Memory Model Feature Register 2

The ID_MMFR2 characteristics are:

Purpose

The ID_MMFR2 provides information about the memory model, memory management, and cache support operations of the processor.

Usage constraints

The ID_MMFR2 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.12.

Figure 4.16 shows the ID_MMFR2 bit assignments.

Figure 4.16. ID_MMFR2 Register bit assignments

Table 4.12 shows the ID_MMFR2 bit assignments.

Table 4.12. ID_MMFR2 bit assignments

Bits

Name Function

Value: 0 [31:28] Hardware access flag

Indicates support for Hardware Access Flag:

0x0 = no support.

Value: 1 [27:24] WFI

Indicates support for Wait-For-Interrupt stalling:

0x1 = the processor supports Wait-For-Interrupt.

Value: 2 [23:20] Memory barrier

Indicates support for memory barrier operations:

0x2 = the processor supports:

DSB (formerly DWB)

ISB (formerly Prefetch Flush)

DMB.

Value: 0 [19:16] TLB maintenance operations (unified)

Indicates support for TLB maintenance operations, unified architecture:

0x0 = no support.

Value: 0 [15:12] TLB maintenance operations (Harvard)

Indicates support for TLB maintenance operations, Harvard architecture:

0x0 = no support.

Value: 0 [11:8] L1 cache maintenance range operations (Harvard)

Indicates support for cache maintenance range operations, Harvard architecture:

0x0 = no support.

Value: 0 [7:4] L1 background prefetch cache operations

Indicates support for background prefetch cache range operations, Harvard architecture:

0x0 = no support.

Value: 0 [3:0] L1 foreground prefetch cache operations

Indicates support for foreground prefetch cache range operations, Harvard architecture:

0x0 = no support.

To access the ID_MMFR2 read CP15 with:

MRC p15, 0, , c0, c1, 6 ; Read ID_MMFR2.

c0, Memory Model Feature Register 3

The ID_MMFR3 characteristics are:

Purpose

Provides information about the two cache line maintenance operations for the processor.

Usage constraints

The ID_MMFR3 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.13.

Figure 4.17 shows the ID_MMFR3 bit assignments.

Figure 4.17. ID_MMFR3 bit assignments

Table 4.13 shows the ID_MMFR3 bit assignments.

Table 4.13. ID_MMFR3 Register bit assignments

Bits

Name

Function

Value: 0 [31:28] Supersection support RAZ because this is a PMSA implementation.

Value: 0 [27:24] - SBZ

Value: 0 [23:20] Coherent walk RAZ because this is a PMSA implementation.

Value: 0 [19:16] - SBZ

Value: 0 [15:12] Maintenance broadcast

Indicates whether cache maintenance operations are broadcast:

0x0 = cache maintenance operations only affect local structures.

Value: 2 [11:8] Branch predictor maintenance operations

Indicates support for branch predictor maintenance operations in systems with hierarchical cache maintenance operations:

0x2 = supports invalidate entire branch predictor array and invalidate branch predictor by MVA[a].

Value: 1 [7:4] Hierarchical cache maintenance operations by Set and Way

Indicates support for hierarchical cache maintenance operations by Set and Way:

0x1 = the processor supports invalidate cache, clean and invalidate, and clean by Set and Way.

Value: 1 [3:0] Hierarchical cache maintenance operations by MVA

Indicates support for hierarchical cache maintenance operations by address:

0x1 = the processor supports:

Invalidate data cache by address

Clean data cache by address

Clean and invalidate data cache by address

Invalidate instruction cache by address

Invalidate all instruction cache entries.

[a] Both of these operations are NOP on Cortex-R4.

To access the ID_MMFR3 read CP15 with:

MRC p15, 0, , c0, c1, 7 ; Read ID_MMFR3.

-----------------------------------

c0, Instruction Set Attributes Register 0

The ID_ISAR0 characteristics are:

Purpose

Provides information about the instruction set that the processor supports, beyond the basic set.

Usage constraints

The ID_ISAR0 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.14.

Figure 4.18 shows the ID_ISAR0 bit assignments.

Figure 4.18. ID_ISAR0 Register bit assignments

Table 4.14 shows the ID_ISAR0 bit assignments.

Table 4.14. ID_ISAR0 Register bit assignments

Bits Name Function

Value: 0 [31:28] -

SBZ

Value: 1 [27:24] Divide instructions

Indicates support for divide instructions:

0x1 = the processor supports SDIV and UDIV instructions.

Value: 1 [23:20] Debug instructions

Indicates support for debug instructions:

0x1 = the processor supports BKPT.

Value: 0 [19:16] Coprocessor instructions

Indicates support for coprocessor instructions other than separately attributed feature registers, such as CP15 registers and VFP:

0x0 = no support.

Value: 1 [15:12] Compare and branch instructions

Indicates support for combined compare and branch instructions:

0x1 = the processor supports combined compare and branch instructions, CBNZ and CBZ.

Value: 1 [11:8] Bitfield instructions

Indicates support for bitfield instructions.

0x1 = the processor supports bitfield instructions, BFC, BFI, SBFX, and UBFX.

Value: 1 [7:4] Bit counting instructions

Indicates support for bit counting instructions.

0x1 = the processor supports CLZ.

Value: 1 [3:0] Atomic instructions

Indicates support for atomic load and store instructions.

0x1 = the processor supports SWP and SWPB.

To access the ID_ISAR0, read CP15 with:

MRC p15, 0, , c0, c2, 0 ; Read ID_ISAR0

c0, Instruction Set Attributes Register 1

The ID_ISAR1 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR1 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.15.

Figure 4.19 shows the ID_ISAR1 bit assignments.

Figure 4.19. ID_ISAR1 Register bit assignments

Table 4.15 shows the ID_ISAR1 bit assignments.

Table 4.15. ID_ISAR1 Register bit assignments

Bits Name Function

Value: 1 [31:28] Jazelle instructions

Indicates support for Jazelle instructions:

0x1 = the processor supports:

BXJ instruction

J bit in PSRs.

For more information see Program status registers and Acceleration of execution environments.

Value: 3 [27:24] Interworking instructions

Indicates support for interworking instructions:

0x3 = the processor supports:

BX, and T bit in PSRs

BLX, and PC loads have BX behavior

data-processing instructions in the ARM instruction set with the PC as the destination and the S bit clear have BX-like behavior.

Value: 1 [23:20] Immediate instructions

Indicates support for immediate instructions:

0x1 = the processor supports:

the MOVT instruction

MOV instruction encodings with 16-bit immediates

Thumb ADD and SUB instructions with 12-bit immediates.

Value: 1 [19:16] ITE instructions

Indicates support for If Then instructions:

0x1 = the processor supports IT instructions.

Value: 2 [15:12] Extend instructions

Indicates support for sign or zero extend instructions:

0x2 = the processor supports:

SXTB, SXTB16, SXTH, UXTB, UXTB16, and UXTH

SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, and UXTAH.

Value: 1 [11:8] Exception 2 instructions

Indicates support for exception 2 instructions:

0x1 = the processor supports RFE, SRS, and CPS.

Value: 1 [7:4] Exception 1 instructions

Indicates support for exception 1 instructions:

0x1 = the processor supports LDM (exception return), LDM (user registers), and STM (user registers).

Value: 1 [3:0] Endian instructions

Indicates support for endianness control instructions:

0x1 = the processor supports SETEND and E bit in PSRs.

To access the ID_ISAR1 read CP15 with:

MRC p15, 0, , c0, c2, 1 ; Read ID_ISAR1

c0, Instruction Set Attributes Register 2

The ID_ISAR2 is:

a read-only register

accessible in Privileged mode only.

The ID_ISAR2 characteristics are:

Purpose

The ID_ISAR2 provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR2 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.16.

Figure 4.20 shows the ID_ISAR2 bit assignments.

Figure 4.20. ID_ISAR2 Register bit assignments

Table 4.16 shows the ID_ISAR2 bit assignments.

Table 4.16. ID_ISAR2 Register bit assignments

Bits

Name Function

Value: 2 [31:28] Reversal instructions

Indicates support for reversal instructions:

0x2 = the processor supports REV, REV16, REVSH, and RBIT.

Value: 1 [27:24] PSR instructions

Indicates support for PSR instructions:

0x1 = the processor supports MRS and MSR, and the exception return forms of data-processing instructions.

Value: 2 [23:20] Unsigned multiply instructions

Indicates support for advanced unsigned multiply instructions:

0x2 = the processor supports:

UMULL and UMLAL

UMAAL.

Value: 3 [19:16] Signed multiply instructions

Indicates support for advanced signed multiply instructions:

0x3 = the processor supports:

SMULL and SMLAL

SMLABB, SMLABT, SMLALBB,SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, and Q flag in PSRs

SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMPUL, SMPULR, SMUAD, SMUADX, SMUSD, and SMUSDX.

Value: 2 [15:12] Multiply instructions

Indicates support for multiply instructions:

0x2 = the processor supports MUL, MLA, and MLS.

Value: 1 [11:8] Interruptible instructions

Indicates support for multi-access interruptible instructions.

0x1 = the processor supports restartable LDM and STM.

Value: 3 [7:4] Memory hint instructions

Indicates support for memory hint instructions.

0x3 = the processor supports PLD and PLI.

Value: 1 [3:0] Load/store instructions

Indicates support for additional load and store instructions.

0x1 = the processor supports LDRD and STRD.

To access the ID_ISAR2 read CP15 with:

MRC p15, 0, , c0, c2, 2 ; Read ID_ISAR2

c0, Instruction Set Attributes Register 3

The ID_ISAR3 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR3 is:

a read-only registers

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.17.

Figure 4.21 shows the ID_ISAR3 bit assignments.

Figure 4.21. ID_ISAR3 Register bit assignments

Table 4.17 shows the ID_ISAR3 bit assignments.

Table 4.17. ID_ISAR3 Register bit assignments

Bits

Name Function

Value: 0 [31:28] ThumbEE extension

Indicates support for ThumbEE Execution Environment extension:

0x0 = no support.

Value: 1 [27:24] True NOP instructions

Indicates support for true NOP instructions:

0x1 = the processor supports NOP16, NOP32 and various NOP compatible hints in both the ARM and Thumb instruction sets.

Value: 1 [23:20] Thumb copy instructions

Indicates support for Thumb copy instructions:

0x1 = the processor supports Thumb MOV(3) low register to low register.

Value: 1 [19:16] Table branch instructions

Indicates support for table branch instructions:

0x1 = the processor supports table branch instructions, TBB and TBH.

Value: 2 [15:12] Synchronization primitive instructions

Indicates support for synchronization primitive instructions:

0x2 = the processor supports:

LDREX and STREX

LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, and CLREX.

Value: 1 [11:8] SVC instructions

Indicates support for SVC (formerly SWI) instructions:

0x1 = the processor supports SVC.

Value: 3 [7:4] SIMD instructions

Indicates support for Single Instruction Multiple Data (SIMD) instructions:

0x3 = the processor supports:

PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UASX, UHSUB16, UHSUB8, USAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT, USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16, and the GE[3:0] bits in the PSRs.

Value: 1 [3:0] Saturate instructions

Indicates support for saturate instructions:

0x1 = the processor supports QADD, QDADD, QDSUB, QSUB and Q flag in PSRs.

To access the ID_ISAR3 read CP15 with:

MRC p15, 0, , c0, c2, 3 ; Read ID_ISAR3

c0, Instruction Set Attributes Register 4

The ID_ISAR4 characteristics are:

Purpose

Provides information about the instruction set that the processor supports beyond the basic set.

Usage constraints

The ID_ISAR4 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.18.

Figure 4.22 shows the ID_ISAR4 bit assignments.

Figure 4.22. ID_ISAR4 Register bit assignments

Table 4.18 shows the ID_ISAR4 bit assignments.

Table 4.18. ISAR4 Register bit assignments

Bits

Name Function

Value: 0 [31:28] SWP_frac RAZ because SWP/SWPB instruction support is indicated in ID_ISAR0.

Value: 0 [27:24] PSR_M_instrs

Indicates support for M-profile instructions for modifying the PSRs:

0x0 = no support.

Value: 0 [23:20] Exclusive instructions

Indicates support for Exclusive instructions:

0x0 = Only supports synchronization primitive instructions as indicated by bits [15:12] in the ISAR3 register. See c0, Instruction Set Attributes Register 3 for more information.

Value: 1 [19:16] Barrier instructions

Indicates support for Barrier instructions:

0x1 = the processor supports DMB, DSB, and ISB instructions.

Value: 0 [15:12] SMC instructions

Indicates support for Secure Monitor Call (SMC) (formerly SMI) instructions:

0x0 = no support.

Value: 1 [11:8] Write-back instructions

Indicates support for write-back instructions:

0x1 = supports all the writeback addressing modes defined in ARMv7.

Value: 4 [7:4] With shift instructions

Indicates support for with-shift instructions:

0x4 = the processor supports:

the full range of constant shift options, on load/store and other instructions

Value: 2 [3:0] Unprivileged instructions

Indicates support for Unprivileged instructions:

0x2 = the processor supports LDR{SB|B|SH|H}T and STR{B|H}T.

To access the ID_ISAR4 read CP15 with:

MRC p15, 0, , c0, c2, 4 ; Read ID_ISAR4

c0, Instruction Set Attributes Register 5

The ID_ISAR5 characteristics are:

Purpose

Provides additional information about the properties of the processor.

Usage constraints

ID_ISAR5 is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

In the processor, ID_ISAR5 is read as 0x00000000.

To access the ID_ISAR5, read CP15 with:

MRC p15, 0, , c0, c2, 5 ; Read ID_ISAR5

c0, Instruction Set Attributes Registers 6-7

ID_ISAR6 and ID_ISAR7 are not implemented, and their positions in the register map are Reserved. They correspond to CP15 accesses with:

MRC p15, 0, , c0, c2, 6 ; Read ID_ISAR6

MRC p15, 0, , c0, c2, 7 ; Read ID_ISAR7

These registers are read-only, and are accessible in Privileged mode only.

------------------------------

4.3.12. c0, Current Cache Size Identification Register

The CCSIDR Register characteristics are:

Purpose

Provides information about the size and behavior of the instruction or data cache. Architecturally, there can be up to eight levels of cache, containing instruction, data, or unified caches. This processor contains L1 instruction and data caches only. The CSSELR determines which CCSIDR to select, see c0, Cache Size Selection Register.

Usage constraints

The CCSIDR is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.19.

Figure 4.23 shows the CCSIDR bit assignments.

Figure 4.23. CCSIDR Register bit assignments

Table 4.19 shows the CCSIDR bit assignments.

Table 4.19. CCSIDR Register bit assignments

Bits

Name Function

Value: 0 [31] WT

Indicates support available for write-through:

1 = write-through support available[a]

Value: 0 [30] WB

Indicates support available for write-back:

1 = write-back support availablea

Value: 0 [29] RA

Indicates support available for read allocation:

1 = read allocation support availablea

Value: 0 [28] WA

Indicates support available for write allocation:

1 = write allocation support availablea

Value: 31(0x1F) [27:13] NumSets

Indicates the number of sets as

(number of sets) - 1a

Value: 3 [12:3] Associativity

Indicates the number of ways as

(number of ways) - 1a

Value: 1 [2:0] LineSize Indicates the number of words in each cache linea

[a] See Table 4.20 for valid bit field encodings.

The LineSize field is encoded as 2 less than log(2) of the number of words in the cache line. For example, a value of 0x0 indicates there are four words in a cache line, that is the minimum size for the cache. A value of 0x1 indicates there are eight words in a cache line.

Table 4.20 shows the individual bit field and complete register encodings for the CCSIDR. Use this to match the cache size and level of cache set by the CSSELR. See c0, Cache Size Selection Register.

Table 4.20. Bit field and register encodings for CCSIDR

Size

Complete register encoding

WT WB RA WA NumSets Associativity LineSize

4KB 0xF003E019 1 1 1 1 0x001F 0x3 0x1

8KB 0xF007E019 1 1 1 1 0x003F

16KB 0xF00FE019 1 1 1 1 0x007F

32KB 0xF01FE019 1 1 1 1 0x00FF

64KB 0xF03FE019 1 1 1 1 0x01FF

To access the CCSIDR read CP15 with:

MRC p15, 1, , c0, c0, 0 ; Read CCSIDR

-----------------------------------------

4.3.13. c0, Current Cache Level ID Register

The CLIDR Register characteristics are:

Purpose

Indicates the cache levels that are implemented. Architecturally, there can be a different number of cache levels on the instruction and data side.

Captures the point-of-coherency.

Captures the point-of-unification.

Usage constraints

The CLIDR is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.21.

Figure 4.24 shows the CLIDR bit assignments.

Figure 4.24. CLIDR Register bit assignments

Table 4.21 shows the CLIDR bit assignments.

Table 4.21. CLIDR Register bit assignments

Bits Name Function

Value: 0 [31:30] - SBZ

Value: 0 [29:27] LoU

Level of Unification:

0b001 = L2, if either cache is implemented

0b000 = L1, if neither instruction nor data cache is implemented.

Value: 0 [26:24] LoC

Level of Coherency:

0b001 = L2, if either cache is implemented

0b000 = L1, if neither instruction nor data cache is implemented.

Value: 0 [23:21] CL 8 0b000 = no cache at Cache Level (CL) 8

Value: 0 [20:18] CL 7 0b000 = no cache at CL 7

Value: 0 [17:15] CL 6 0b000 = no cache at CL 6

Value: 0 [14:12] CL 5 0b000 = no cache at CL 5

Value: 0 [11:9] CL 4 0b000 = no cache at CL 4

Value: 0 [8:6] CL 3 0b000 = no cache at CL 3

Value: 0 [5:3] CL 2 0b000 = no cache at CL 2

Value: 0 [2] CL 1 RAZ. Indicates no unified cache at CL1

Value: 0 [1] CL 1

0b000 = no data cache is implemented

0b001 = data cache is implemented.

Value: 0 [0] CL 1

0b000 = no instruction cache is implemented.

0b001 = an instruction cache is implemented.

To access the CLIDR, read CP15 with:

MRC p15, 1, , c0, c0, 1 ; Read CLIDR

------------------------------------------------

4.3.14. c0, Cache Size Selection Register

The CSSELR characteristics are:

Purpose

Holds the value that the processor uses to select the CSSELR to use.

Usage constraints

The CSSELR is:

a read/write register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.22.

Figure 4.25 shows the CSSELR bit assignments.

Figure 4.25. CSSELR Register bit assignments

Table 4.22 shows the CSSELR bit assignments.

Table 4.22. CSSELR Register bit assignments

Bits

Name Function

Value: 0 [31: 4] - SBZ.

Value: 0 [3:1] Level

Identifies which cache level to select:

b000 = L1 cache

This field is read only, writes are ignored.

Value: 0 [0] InD

Identifies instruction or data cache to use:

1 = instruction

0 = data.

To access the CCSIDRs read or write CP15 with:

MRC p15, 2, , c0, c0, 0 ; Read CSSELR

MCR p15, 2, , c0, c0, 0 ; Write CSSELR

---------------------------------------------------

4.3.15. c1, System Control Register

The SCTLR characteristics are:

Purpose

Provides control and configuration information for:

memory alignment, endianness, protection, and fault behavior

MPU and cache enables and cache replacement strategy

interrupts and the behavior of interrupt latency

the location for exception vectors

program flow prediction.

Usage constraints

The SCTLR is:

a read/write register

accessible in Privileged mode only

attempts to read or write the SCTLR from User mode result in an Undefined Instruction exception.

Configurations

Available in all processor configurations.

Attributes

See Table 4.23.

Figure 4.26 shows the SCTLR bit assignments.

Figure 4.26. SCTLR Register bit assignments

Table 4.23 shows the SCTLR bit assignments.

Table 4.23. SCTLR Register bit assignments

Bits

Name

Function

Value: 0 [31]

Identifies little or big instruction endianness in use:

0 = little-endianness

1 = big-endianness.

The primary input CFGIE defines the reset value. This bit is read-only.

Value: 0 [30] TE

Thumb exception enable:

0 = enable ARM exception generation

1 = enable Thumb exception generation.

The primary input TEINIT defines the reset value.

Value: 0 [29] AFE Access Flag Enable. On the processor this bit is SBZ.

Value: 0 [28] TRE TEX Remap Enable. On the processor this bit is SBZ.

Value: 0 [27]

NMFI

NMFI, non-maskable fast interrupt enable:

0 = Software can disable FIQs

1 = Software cannot disable FIQs.

This bit is read-only. The configuration input CFGNMFI defines its value.

Value: 0 [26] - SBZ.

Value: 0 [25] EE

Determines how the E bit in the CPSR is set on an exception:

0 = CPSR E bit is set to 0 on an exception

1 = CPSR E bit is set to 1 on an exception.

The primary input CFGEE defines the reset value.

Value: 0 [24] VE

Configures vectored interrupt:

0 = exception vector address for IRQ is 0x00000018 or 0xFFFF0018. See V bit.

1 = VIC controller provides handler address for IRQ.

The reset value of this bit is 0.

Value: 1 [23:22] -

SBO.

Value: 0 [21] FI

Fast Interrupts enable.

On the processor Fast Interrupts are always enabled. This bit is SBO.

Value: 0 [20] - SBZ.

Value: 0 [19] DZ

Divide by zero:

0 = do not generate an Undefined Instruction exception

1 = generate an Undefined Instruction exception.

The reset value of this bit is 0.

Value: 0 [18] - SBO.

Value: 0 [17] BR MPU background region enable.

Value: 0 [16] - SBO.

Value: 0 [15] - SBZ.

Value: 0 [14] RR

Round-robin bit, controls replacement strategy for instruction and data caches:

0 = random replacement strategy

1 = round-robin replacement strategy.

The reset value of this bit is 0. The processor always uses a random replacement strategy, regardless of the state of this bit.

Value: 0 [13]

Determines the location of exception vectors:

0 = normal exception vectors selected, address range = 0x00000000-0x0000001C

1 = high exception vectors (HIVECS) selected, address range = 0xFFFF0000-0xFFFF001C.

The primary input VINITHI defines the reset value.

Value: 0 [12]

Enables L1 instruction cache:

0 = instruction caching disabled. This is the reset value.

1 = instruction caching enabled.

If no instruction cache is implemented, then this bit is SBZ.

Value: 0 [11] Z

Branch prediction enable bit.

The processor supports branch prediction. This bit is SBO. The ACTLR can control branch prediction, see c1, Auxiliary Control Register.

Value: 0 [10:7] - SBZ.

Value: 7 [6:3] - SBO.

Value: 0 [2]

Enables L1 data cache:

0 = data caching disabled. This is the reset value.

1 = data caching enabled.

If no data cache is implemented, then this bit is SBZ.

Value: 0 [1]

Enables strict alignment of data to detect alignment faults in data accesses:

0 = strict alignment fault checking disabled. This is the reset value.

1 = strict alignment fault checking enabled.

Value: 0 [0]

Enables the MPU:

0 = MPU disabled. This is the reset value.

1 = MPU enabled.

If no MPU is implemented, this bit is SBZ.

To use the SCTLR, ARM recommends that you use a read-modify-write technique. To access the SCTLR, read or write CP15 with:

MRC p15, 0, , c1, c0, 0 ; Read SCTLR

MCR p15, 0, , c1, c0, 0 ; Write SCTLR

-----------------------------------

4.3.16. c1, Auxiliary Control Register

The ACTLR characteristics are:

Purpose

Controls:

branch prediction

performance features

error and parity logic.

Usage constraints

The ACTLR is:

a read/write register

accessible in Privileged mode only

ARM recommends that any instruction that changes bits [31:28] or [7] is followed by an ISB instruction to ensure that the changes have taken effect before any dependent instructions are executed.

Configurations

Available in all processor configurations.

Attributes

See Table 4.24.

Figure 4.27 shows the ACTLR bit assignments.

Figure 4.27. ACTLR Register bit assignments

Table 4.24 shows the ACTLR bit assignments.

Table 4.24. ACTLR Register bit assignments

Bits

Name Function

Value: 0 [31] DICDI[a]

Case C dual issue control:

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [30] DIB2DI[a]

Case B2 dual issue control:

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [29] DIB1DI[a]

Case B1 dual issue control:

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [28] DIADI[a]

Case A dual issue control:

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [27] B1TCMPCEN

B1TCM parity or ECC check enable:

0 = Disabled

1 = Enabled.

The primary input PARECCENRAM[2][b] defines the reset value.

If the BTCM is configured with ECC, you must always set this bit to the same value as B0TCMPCEN.

Value: 0 [26] B0TCMPCEN

B0TCM parity or ECC check enable:

0 = Disabled

1 = Enabled.

The primary input PARECCENRAM[1][b] defines the reset value.

If the BTCM is configured with ECC, you must always set this bit to the same value as B1TCMPCEN.

Value: 0 [25] ATCMPCEN

ATCM parity or ECC check enable:

0 = Disabled

1 = Enabled.

The primary input PARECCENRAM[0][b] defines the reset value.

Value: 0 [24] AXISCEN

AXI slave cache RAM access enable:

0 = Disabled. This is the reset value.

1 = Enabled.

Note

When AXI slave cache access is enabled, the caches are disabled and the processor cannot run any cache maintenance operations. If the processor attempts a cache maintenance operation, an Undefined Instruction exception is taken.

Value: 0 [23] AXISCUEN

AXI slave cache RAM non-privileged access enable:

0 = Disabled. This is the reset value.

1 = Enabled.

Value: 0 [22] DILSM

Disable Low Interrupt Latency (LIL) on load/store multiples:

0 = Enable LIL on load/store multiples. This is the reset value.

1 = Disable LIL on all load/store multiples.

Value: 0 [21] DEOLP

Disable end of loop prediction:

0 = Enable loop prediction. This is the reset value.

1 = Disable loop prediction.

Value: 0 [20] DBHE

Disable Branch History (BH) extension:

0 = Enable the extension. This is the reset value.

1 = Disable the extension.

Value: 0 [19] FRCDIS

Fetch rate control disable:

0 = Normal fetch rate control operation. This is the reset value.

1 = Fetch rate control disabled.

Value: 0 [18] - SBZ.

Value: 0 [17] RSDIS

Return stack disable:

0 = Normal return stack operation. This is the reset value.

1 = Return stack disabled.

Value: 0 [16:15] BP

This field controls the branch prediction policy:

b00 = Normal operation. This is the reset value.

b01 = Branch always taken.

b10 = Branch always not taken.

b11 = Reserved. Behavior is Unpredictable if this field is set to b11.

Value: 0 [14] DBWR

Disable write burst in the AXI master:

0 = Normal operation. This is the reset value.

1 = Disable write burst optimization.

Value: 0 [13] DLFO

Disable linefill optimization in the AXI master:

0 = Normal operation. This is the reset value.

1 = Limits the number of outstanding data linefills to two.

Value: 0 [12] ERPEG[c]

Enable random parity error generation:

0 = Random parity error generation disabled. This is the reset value.

1 = Enable random parity error generation in the cache RAMs.

Note

This bit controls error generation logic during system validation. A synthesized ASIC typically does not have such models and this bit is therefore redundant for ASICs.

Value: 0 [11] DNCH

Disable data forwarding for Non-cacheable accesses in the AXI master:

0 = Normal operation. This is the reset value.

1 = Disable data forwarding for Non-cacheable accesses.

Value: 0 [10] FORA

Force outer read allocate (ORA) for outer write allocate (OWA) regions:

0 = No forcing of ORA. This is the reset value.

1 = ORA forced for OWA regions.

Value: 0 [9] FWT

Force write-through (WT) for write-back (WB) regions:

0 = No forcing of WT. This is the reset value.

1 = WT forced for WB regions.

Value: 0 [8] FDSnS

Force data side to not-shared when MPU is off:

0 = Normal operation. This is the reset value.

1 = Data side normal Non-cacheable forced to Non-shared when MPU is off.

Value: 0 [7] sMOV

sMOV of a divide does not complete out of order. No other instruction is issued until the divide is finished.

0 = Normal operation. This is the reset value.

1 = sMOV out of order disabled.

Value: 0 [6] DILS

Disable low interrupt latency on all load/store instructions.

0 = Enable LIL on all load/store instructions. This is the reset value.

1 = Disable LIL on all load/store instructions.

Value: 0 [5:3] CEC

Cache error control for cache parity and ECC errors.

See Table 8.2 and Table 8.3 for information about how these bits are used. The reset value is b100.

Value: 0 [2] B1TCMECEN

B1TCM external error enable:

0 = Disabled

1 = Enabled.

The primary input ERRENRAM[2] defines the reset value.

Value: 0 [1] B0TCMECEN

B0TCM external error enable:

0 = Disabled

1 = Enabled.

The primary input ERRENRAM[1] defines the reset value.

Value: 0 [0] ATCMECEN

ATCM external error enable:

0 = Disabled

1 = Enabled.

The primary input ERRENRAM[0] defines the reset value.

[a] See Dual issue

[b] See Configuration signals.

[c] This bit is only supported if parity error generation is implemented in your design.

To access the ACTLR, read or write CP15 with:

MRC p15, 0, , c1, c0, 1 ; Read ACTLR

MCR p15, 0, , c1, c0, 1 ; Write ACTLR

-------------------------------

4.3.17. c15, Secondary Auxiliary Control Register

The Secondary Auxiliary Control Register characteristics are:

Purpose

Controls:

branch prediction

performance features

error and parity logic.

Usage constraints

The Secondary Auxiliary Control Register is:

a read/write register

accessible in Privileged mode only.

ARM recommends that any instruction that changes bits [20:16] is followed by an ISB instruction to ensure that the changes have taken effect before any dependent instructions are executed.

Configurations

Available in all processor configurations.

Attributes

See Table 4.25.

Note

This register is implemented from the r1pn releases of the processor. Attempting to access this register in r0pn releases of the processor results in an Undefined Instruction exception.

Figure 4.28 shows the Secondary Auxiliary Control Register bit assignments.

Figure 4.28. Secondary Auxiliary Control Register bit assignments

Table 4.25 shows the Secondary Auxiliary Control Register bit assignments.

Table 4.25. Secondary Auxiliary Control Register bit assignments

Bits Name Function

Value: 0 [31:23] - SBZ.

Value: 0 [22] DCHE

Disable hard-error support in the caches:[a]

0 = Enabled. The cache logic recovers from some hard errors. You must not use this value on revisions r1p2 or earlier of the processor.

1 = Disabled. Most hard errors in the caches are fatal. This is the reset value.

See Hard errors for more information.

Value: 0 [21] DR2B[b]

Enable random 2-bit error generation in cache RAMs. This bit has no effect unless ECC is configured, see Configurable options:

0 = Disabled. This is the reset value.

1 = Enabled.

Note

This bit controls error generation logic during system validation. A synthesized ASIC typically does not have such models and this bit is therefore redundant for ASICs.

Value: 0 [20] DF6DI

F6 dual issue control:[c]

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [19] DF2DI

F2_Id/F2_st/F2D dual issue control:[c]

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [18] DDI

F1/F3/F4dual issue control:[c]

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [17] DOODPFP

Out-of-order Double Precision Floating Point instruction control:[c]

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [16] DOOFMACS

Out-of-order FMACS control:[c]

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [15:14] - SBZ.

Value: 0 [13] IXC

Floating-point inexact exception output mask::[c]

0 = Mask floating-point inexact exception output. The output FPIXC is forced to zero. This is the reset value.

1 = Propagate floating point inexact exception flag FPSCR.IXC to output FPIXC.

Value: 0 [12] OFC

Floating-point overflow exception output mask:[c]

0 = Mask floating-point overflow exception output. The output FPOFC is forced to zero. This is the reset value.

1 = Propagate floating-point overflow exception flag FPSCR.OFC to output FPOFC.

Value: 0 [11] UFC

Floating-point underflow exception output mask:[c]

0 = Mask floating-point underflow exception output. The output FPUFC is forced to zero. This is the reset value.

1 = Propagate floating-point underflow exception flag FPSCR.UFC to output FPUFC.

Value: 0 [10] IOC

Floating-point invalid operation exception output mask:[c]

0 = Mask floating-point invalid operation exception output. The output FPIOC is forced to zero. This is the reset value.

1 = Propagate floating-point invalid operation exception flag FPSCR.IOC to output FPIOC.

Value: 0 [9] DZC

Floating-point divide-by-zero exception output mask:[c]

0 = Mask floating-point divide-by-zero exception output. The output FPDZC is forced to zero. This is the reset value.

1 = Propagate floating-point divide-by-zero exception flag FPSCR.DZC to output FPDZC.

Value: 0 [8] IDC

Floating-point input denormal exception output mask:[c]

0 = Mask floating-point input denormal exception output. The output FPIDC is forced to zero. This is the reset value.

1 = Propagate floating-point input denormal exception flag FPSCR.IDC to output FPIDC.

Value: 0 [7:4] - SBZ.

Value: 0 [3] BTCMECC

Correction for internal ECC logic on BTCM ports:[d]

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [2] ATCMECC

Correction for internal ECC logic on ATCM port:[d]

0 = Enabled. This is the reset value.

1 = Disabled.

Value: 0 [1] BTCMRMW

Enables 64-bit stores for the BTCMs. When enabled, the processor uses read-modify-write to ensure that all reads and writes presented on the BTCM ports are 64 bits wide:[e]

0 = Disabled

1 = Enabled.

The primary input RMWENRAM[1] defines the reset value.

Value: 0 [0] ATCMRMW

Enables 64-bit stores for the ATCM. When enabled, the processor uses read-modify-write to ensure that all reads and writes presented on the ATCM port are 64 bits wide:[e]

0 = Disabled

1 = Enabled.

The primary input RMWENRAM[0] defines the reset value.

[a] This bit is RAZ if both caches have neither ECC nor parity.

[b] This bit is only supported if parity error generation is implemented in your design.

[c] This bit has no effect unless the Floating Point Unit (FPU) is configured, see Configurable options.

[d] This bit has no effect unless TCM ECC logic is configured for the respective TCM interface, see Configurable options.

[e] This feature is not available when the TCM interface is built with 32-bit ECC.

To access the Secondary Auxiliary Control Register, read or write CP15 with:

MRC p15, 0, , c15, c0, 0 ; Read Secondary Auxiliary Control Register

MCR p15, 0, , c15, c0, 0 ; Write Secondary Auxiliary Control Register

----------------------------------------

4.3.18. c1, Coprocessor Access Register

The CPACR characteristics are:

Purpose

Sets access rights for coprocessors.

Usage constraints

The CPACR is:

A read/write register.

Accessible in Privileged mode only.

Because this processor does not support coprocessors CP0-CP9, CP12, and CP13, bits [27:24] and [19:0] in this register are read-as-zero and ignore writes.

CPACR has no effect on access to CP14, the debug control coprocessor, or CP15, the system control coprocessor. The only other coprocessor that the Cortex-R4F processor includes is the FPU, CP10, and CP11. This register enables software to determine if the FPU exists in the processor.

Configurations

Available in all processor configurations.

Attributes

See Table 4.26.

Figure 4.29 shows the CPACR bit assignments.

Figure 4.29. CPACR Register bit assignments

Table 4.26 shows the CPACR bit assignments.

Table 4.26. CPACR Register bit assignments

Bits

Name Function

Value: 0 [31:28] - SBZ.

Value: 0 [27:0] cp[a]

Defines access permissions for each coprocessor

Access denied is the reset condition, and is the behavior for non-existent coprocessors:

b00 = Access denied. Attempts to access generates an Undefined Instruction exception.

b01 = Privileged mode access only

b10 = Reserved

b11 = Privileged and User mode access.

Access permissions for the FPU are set by fields cp10 and cp11. For all other coprocessor fields, the value is fixed to b00.

[a] n is the coprocessor number between 0 and 13.

To access the CPACR, read or write CP15 with:

MRC p15, 0, , c1, c0, 2 ; Read CPACR

MCR p15, 0, , c1, c0, 2 ; Write CPACR

--------------------------------------------

c5, Data Fault Status Register

The DFSR characteristics are:

Purpose

Holds status information regarding the source of the last data abort.

Usage constraints

The DFSR is:

a read/write register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.28.

Figure 4.30 shows the DFSR bit assignments.

Figure 4.30. DFSR Register bit assignments

Table 4.28 shows the DFSR bit assignments.

Table 4.28. DFSR Register bit assignments

Bits

Name Function

Value: 0 [31:13]

- SBZ.

Value: 0 [12]

Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for external aborts. For all other aborts types of abort, this bit is set to zero:

0 = AXI Decode error (DECERR) caused the abort

1 = AXI Slave error (SLVERR, or OKAY in response to exclusive read transaction) caused the abort.

Value: 0 [11]

Indicates whether a read or write access caused an abort:

0 = read access caused the abort

1 = write access caused the abort.

[10][a]

Part of the Status field.

Value: 0 [9:8]

Always RAZ. Writes ignored.

Value: 0 [7:4]

Domain SBZ. This is because domains are not implemented in this processor.

[3:0][a]

Status

Indicates the type of fault generated. To determine the data fault, you must use bit [12] and bit [10] in conjunction with bits [3:0].

[a] For more information on how these bits are used in reporting faults, see Table 4.27.

To use the DFSR read or write CP15 with:

MRC p15, 0, , c5, c0, 0 ; Read DFSR

MCR p15, 0, , c5, c0, 0 ; Write DFSR

c5, Instruction Fault Status Register

The IFSR characteristics are:

Purpose

Holds status information regarding the source of the last instruction abort.

Usage constraints

The IFSR is:

a read/write register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.29.

Figure 4.31 shows the IFSR bit assignments.

Figure 4.31. IFSR Register bit assignments

Table 4.29 shows the IFSR bit assignments.

Table 4.29. IFSR Register bit assignments

Bits Name Function

Value: 0 [31:13] - SBZ.

Value: 0 [12] SD

Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for external aborts. For all other aborts types of abort, this bit is set to zero:

0 = AXI Decode error (DECERR) caused the abort

1 = AXI Slave error (SLVERR) caused the abort.

Value: 0 [11] - SBZ.

[10][a] S

Part of the Status field.

Value: 0 [9:8] - SBZ.

Value: 0 [7:4] Domain SBZ. This is because domains are not implemented in this processor.

[3:0][a] Status

Indicates the type of fault generated. To determine the instruction fault, bit [12] and bit [10] must be used in conjunction with bits [3:0].

[a] For more information on how these bits are used in reporting faults, see Table 4.27.

To access the IFSR read or write CP15 with:

MRC p15, 0, , c5, c0, 1 ; Read IFSR

MCR p15, 0, , c5, c0, 1 ; Write IFSR

c5, Auxiliary Fault Status Registers

The processor has two auxiliary fault status registers:

the Auxiliary Data Fault Status Register (ADFSR)

the Auxiliary Instruction Fault Status Register (AIFSR).

The auxiliary fault status registers characteristics are:

Purpose

Provide additional information about data and instruction parity, ECC, and external TCM errors.

Usage constraints

The auxiliary fault status registers are:

Read/write registers.

Accessible in Privileged mode only.

The contents of an auxiliary fault status register are only valid when the corresponding Data or Instruction Fault Status Register indicates that a parity or ECC error has occurred. At other times the contents of the auxiliary fault status registers are Unpredictable.

Configurations

Available in all processor configurations.

Attributes

See Table 4.30.

Figure 4.32 shows the auxiliary fault status register bit assignments.

Figure 4.32. Auxiliary fault status register bit assignments

Table 4.30 shows the auxiliary fault status register bit assignments.

Table 4.30. Auxiliary fault status register bit assignments

Bits Name Function

Value: 0 [31:28] - SBZ.

Value: 0 [27:24] CacheWay[a]

The value returned in this field indicates the cache way or ways in which the error occurred.

Value: 0 [23:22] Side

The value returned in this field indicates the source of the error. Possible values are:

b00 = Cache or AXI master interface

b01 = ATCM

b10 = BTCM

b11 = Reserved.

Value: 0 [21] Recoverable error

The value returned in this field indicates if the error is recoverable:

0 = Unrecoverable error.

1 = Recoverable error. This includes all correctable parity/ECC errors and recoverable TCM external errors.

Value: 0 [20:14] - SBZ.

Value: 0 [13:5] Index[b]

This field returns the index value for the access giving the error.

Value: 0 [4:0] - SBZ.

[a] This field is only valid for data cache store parity/ECC errors, otherwise it is Unpredictable.

[b] This field is only valid for data cache store parity/ECC errors. On the AIFSR, and for TCM accesses, this field SBZ.

To access the auxiliary fault status registers, read or write CP15 with:

MCR p15, 0, , c5, c1, 0 ; Write ADFSR

MRC p15, 0, , c5, c1, 0 ; Read ADFSR

MCR p15, 0, , c5, c1, 1 ; Write AIFSR

MRC p15, 0, , c5, c1, 1 ; Read AIFSR

c6, Data Fault Address Register

The DFAR characteristics are:

Purpose

Holds the address of the fault when a synchronous abort occurs.

Usage constraints

The DFAR is:

a read/write register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

The DFAR bits [31:0] contain the address where the synchronous abort occurred.

To access the DFAR read or write CP15 with:

MRC p15, 0, , c6, c0, 0 ; Read DFAR

MCR p15, 0, , c6, c0, 0 ; Write DFAR

A write to this register sets the DFAR to the value of the data written. This is useful for a debugger to restore the value of the DFAR.

The processor also updates the DFAR on debug exception entry because of watchpoints. See Effect of debug exceptions on CP15 registers and DBGWFAR for more information.

c6, Instruction Fault Address Register

The IFAR characteristics are:

Purpose

Holds the address of the instruction that caused a prefetch abort.

Usage constraints

The IFAR is:

a read/write register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

The IFAR bits [31:0] contain the Instruction Fault address.

To access the IFAR read or write CP15 with:

MRC p15, 0, , c6, c0, 2 ; Read IFAR

MCR p15, 0, , c6, c0, 2 ; Write IFAR

A write to this register sets the IFAR to the value of the data written. This is useful for a debugger to restore the value of the IFAR.

-----------------------------------

4.3.20. c6, MPU memory region programming registers

The MPU memory region programming registers program the MPU regions.

There is one register that specifies which one of the sets of region registers is to be accessed. See c6, MPU Memory Region Number Register. Each region has its own register status to specify:

region base address

region size and enable

region access control.

You can implement the processor with 12 or 16 regions, or without an MPU entirely. If you implement the processor without an MPU, then there are no regions and no region programming registers.

Note

When the MPU is enabled:

The MPU determines the access permissions for all accesses to memory, including the TCMs. Therefore, you must ensure that the memory regions in the MPU are programmed to cover the complete TCM address space with the appropriate access permissions. You must define at least one of the regions in the MPU.

An access to an undefined area of memory normally generates a background fault.

For the TCM space the processor uses the access permissions but ignores the region attributes from MPU.

CP15, c9 sets the location of the TCM base address. For more information see c9, BTCM Region Register and c9, ATCM Region Register.

c6, MPU Region Base Address Registers

The MPU Region Base Address Register characteristics are:

Purpose

Describes the base address of the region specified by the Memory Region Number Register.

Usage constraints

The MPU Region Base Address Registers are:

32-bit read/write registers

accessible in Privileged mode only.

The region base address must always align to the region size.

Configurations

Use these registers if the processor is configured with an MPU.

Attributes

See Table 4.31.

Figure 4.33 shows the MPU Region Base Address Registers bit assignments.

Figure 4.33. MPU Region Base Address Registers bit assignments

Table 4.31 shows the MPU Region Base Address Registers bit assignments.

Table 4.31. MPU Region Base Address Registers bit assignments

Bits

Name Function

Value: 33558528(0x2001000) [31:5] Base address Defines bits [31:5] of the base address of a region.

Value: 0 [4:0] - SBZ

To access an MPU Region Base Address Register, read or write CP15 with:

MRC p15, 0, , c6, c1, 0 ; Read MPU Region Base Address Register

MCR p15, 0, , c6, c1, 0 ; Write MPU Region Base Address Register

c6, MPU Region Size and Enable Registers

The MPU Region Size and Enable Register characteristics are:

Purpose

Specifies the size of the region specified by the Memory Region Number Register.

Identifies the address ranges that are used for a particular region.

Enables or disables the region, and its sub-regions, specified by the Memory Region Number Register.

Usage constraints

The MPU Region Size and Enable Registers are:

32-bit read/write registers

accessible in Privileged mode only.

Configurations

Use these registers if the processor is configured with an MPU.

Attributes

See Table 4.32.

Figure 4.34 shows the MPU Region Size and Enable Registers bit assignments.

Figure 4.34. MPU Region Size and Enable Registers bit assignments

Table 4.32 shows the MPU Region Size and Enable Registers bit assignments.

Table 4.32. Region Size MPU Region Size and Enable Registers bit assignments

Bits Name Function

Value: 0 [31:16] - SBZ.

Value: 0 [15:8] Sub-region disable

Each bit position represents a sub-region, 0-7[a].

Bit [8] corresponds to sub-region 0

...

Bit [15] corresponds to sub-region 7

The meaning of each bit is:

0 = address range is part of this region

1 = address range is not part of this region.

- SBZ.

Value: 0 [5:1] Region size

Defines the region size:

b00000 - b00011=Unpredictable

b00100 = 32 bytes

b00101 = 64 bytes

b00110 = 128 bytes

b00111 = 256 bytes

b01000 = 512 bytes

b01001 = 1KB

b01010 = 2KB

b01011 = 4KB

b01100 = 8KB

b01101 = 16KB

b01110 = 32KB

b01111 = 64KB

b10000 = 128KB

b10001 = 256KB

b10010 = 512KB

b10011 = 1MB

b10100 = 2MB

b10101 = 4MB

b10110 = 8MB

b10111 = 16MB

b11000 = 32MB

b11001 = 64MB

b11010 = 128MB

b11011 = 256MB

b11100 = 512MB

b11101 = 1GB

b11110 = 2GB

b11111 = 4GB.

Value: 0 [0]

Enable

Enables or disables a memory region:

0 = Memory region disabled. Memory regions are disabled on reset.

1 = Memory region enabled. A memory region must be enabled before it is used.

[a] Sub-region 0 covers the least significant addresses in the region, while sub-region 7 covers the most significant addresses in the region. For more information, see Subregions.

To access an MPU Region Size and Enable Register, read or write CP15 with:

MRC p15, 0, , c6, c1, 2 ; Read Data MPU Region Size and Enable Register

MCR p15, 0, , c6, c1, 2 ; Write Data MPU Region Size and Enable Register

Writing a region size that is outside the range results in Unpredictable behavior.

c6, MPU Region Access Control Registers

The MPU Region Access Control Register characteristics are:

Purpose

Holds the region attributes and access permissions for the region specified by the Memory Region Number Register.

Usage constraints

The MPU Region Access Control Registers are:

read/write registers

accessible in Privileged mode only.

Configurations

Use these registers if the processor is configured with an MPU.

Attributes

See Table 4.33.

Figure 4.35 shows the MPU Region Access Control Registers bit assignments.

Figure 4.35. MPU Region Access Control Register bit assignments

Table 4.33 shows the MPU Region Access Control Registers bit assignments.

Table 4.33. MPU Region Access Control Register bit assignments

Bits

Name Function

Value: 0 [31:13]

- SBZ.

Value: 0 [12] XN

eXecute Never. Determines if a region of memory is executable:

0 = all instruction fetches enabled

1 = no instruction fetches enabled.

Value: 0 [11] - Reserved.

Value: 2 [10:8] AP Access permission. Defines the data access permissions. For more information on AP bit values see, Table 4.36.

Value: 0 [7:6] - SBZ.

Value: 1 [5:3] TEX Type extension. Defines the type extension attribute[a].

Value: 0 [2] S

Share. Determines if the memory region is Shared or Non-shared:

0 = Non-shared.

1 = Shared.

This bit only applies to Normal, not Device or Strongly-ordered memory.

Value: 0 [1] C

C bit[a]:

Value: 0 [0] B

B bit[a]:

[a] For more information on this region attribute, see Table 4.34.

Table 4.34 shows the encoding for the TEX[2:0], C, and B regions.

Table 4.34. TEX[2:0], C, and B encodings

TEX[2:0] C B Description Memory Type Shareable?

000 0 0 Strongly-ordered. Strongly-ordered Shareable

000 0 1 Shareable Device. Device Shareable

000 1 0 Outer and Inner write-through, no write-allocate. Normal S bit[a]

000 1 1 Outer and Inner write-back, no write-allocate.[b] Normal S bit[a]

001 0 0 Outer and Inner Non-cacheable. Normal S bit[a]

001 0 1 Reserved. - -

001 1 0

001 1 1 Outer and Inner write-back, write-allocate. Normal S bit[a]

010 0 0 Non-shareable Device. Device Non-shareable

010 0 1 Reserved. - -

010 1 X Reserved. - -

011 X X Reserved. - -

1BB A A

Cacheable memory:

AA[c] = Inner policy

BB[c] = Outer policy

Normal

S bit[a]

[a] Region is Shareable if S == 1, and Non-shareable if S == 0.

[b] If the memory region type is specified as Write back cacheable (no write-allocate), memory accesses to this type of memory behave as Write Back Write Allocate behavior for a memory.

[c] Table 4.35 shows the encoding for these bits.

When TEX[2] == 1, the memory region is cacheable memory, and the rest of the encoding defines the Inner and Outer cache policies:

TEX[1:0]

Defines the Outer cache policy.

C,B

Defines the Inner cache policy.

The same encoding is used for the Outer and Inner cache policies. Table 4.35 shows the encoding.

Table 4.35. Inner and Outer cache policy encoding

Memory attribute encoding Cache policy

00 Non-cacheable

01 Write-back, write-allocate

10 Write-through, no write-allocate

11 Write-back, no write-allocate

Table 4.36 shows the AP bit values that determine the permissions for Privileged and User data access.

Table 4.36. Access data permission bit encoding

AP bit values Privileged permissions User permissions Description

b000 No access No access

All accesses generate a permission fault

b001 Read/write No access

Privileged access only

b010 Read/write Read-only

Writes in User mode generate permission faults

b011 Read/write Read/write

Full access

b100 UNP UNP

Reserved

b101 Read-only No access

Privileged read-only

b110 Read-only Read-only

Privileged/User read-only

b111 UNP UNP

Reserved

To access the MPU Region Access Control Registers read or write CP15 with:

MRC p15, 0, , c6, c1, 4 ; Read Region access control Register

MCR p15, 0, , c6, c1, 4 ; Write Region access control Register

To execute instructions in User and Privileged modes:

the region must have read access as defined by the AP bits

the XN bit must be set to 0.

c6, MPU Memory Region Number Register

The RGNRs characteristics are:

Purpose

Multiple registers with one register for each memory region implemented. The value contained in the RGNR determines which of the multiple registers is accessed.

Usage constraints

The RGNRs are:

Read/write register.

Accessible in Privileged mode only.

Writing this register with a value greater than or equal to the number of regions from the MPUIR is Unpredictable. Associated MPU Region Register accesses are also Unpredictable.

Configurations

Use this register if the processor is configured with an MPU.

Attributes

See Table 4.37.

Figure 4.36 shows the RGNR bit assignments.

Figure 4.36. RGNR Register bit assignments

Table 4.37 shows the RGNR bit assignments.

Table 4.37. RGNR Register bit assignments

Bits

Name Function

Value: 0 [31:4] - SBZ.

Value: 0 [3:0] Region Defines the group of registers to be accessed. Read the MPUIR to determine the number of supported regions, see c0, MPU Type Register.

To access the RGNR, read or write CP15 with:

MRC p15, 0, , c6, c2, 0 ; Read RGNR

MCR p15, 0, , c6, c2, 0 ; Write RGNR

Writing this register with a value greater than or equal to the number of regions from the MPUIR is Unpredictable. Associated MPU Region Register accesses are also Unpredictable.

----------------------------------

4.3.22. c9, BTCM Region Register

The BTCM Region Register characteristics are:

Purpose

Holds the base address and size of the BTCM.

Determines if the BTCM is enabled.

Usage constraints

The BTCM Region Register is:

a read/write register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.41.

Figure 4.40 shows the BTCM Region Register bit assignments.

Figure 4.40. BTCM Region Register bit assignments

Table 4.41 shows the BTCM Region Register bit assignments.

Table 4.41. BTCM Region Register bit assignments

Bits

Name

Function

Value: 2048(0x800) [31:12]

Base address

Base address. Defines the base address of the BTCM. The base address must be aligned to the size of the BTCM. Any bits in the range [(log2(RAMSize)-1):12] are ignored.

At reset, if LOCZRAMA is set to:

0 =The initial base address is 0x0.

1 =The initial base address is implementation-defined. See Configurable options.

Value: 0 [11:7] - UNP on reads, SBZ on writes.

Value: 14(0xE) [6:2] Size Size. Indicates the size of the BTCM on reads. On writes this field is ignored. See About the TCMs:

b00000 = 0KB

b00011 = 4KB

b00100 = 8KB

b00101 = 16KB

b00110 = 32KB

b00111 = 64KB

b01000 = 128KB

b01001 = 256KB

b01010 = 512kB

b01011 = 1MB

b01100 = 2MB

b01101 = 4MB

b01110 = 8MB

Value: 0 [1] - SBZ.

Value: 0 [0]

Enable

Enables or disables the BTCM:

0 = Disabled

1 = Enabled. The reset value of this field is determined by the INITRAMB input pin.

To access the BTCM Region Register, read or write CP15 with:

MRC p15, 0, , c9, c1, 0 ; Read BTCM Region Register

MCR p15, 0, , c9, c1, 0 ; Write BTCM Region Register

-----------------------------------

4.3.23. c9, ATCM Region Register

The ATCM Region Register characteristics are:

Purpose

Holds the base address and size of the ATCM.

Determines if the ATCM is enabled.

Usage constraints

The ATCM Region Register is:

a read/write register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.42.

Figure 4.41 shows the ATCM Region Register bit assignments.

Figure 4.41. ATCM Region Register bit assignments

Table 4.42 shows the ATCM Region Register bit assignments.

Table 4.42. ATCM Region Register bit assignments

Bits

Name

Function

Value: 0 [31:12]

Base address

Base address. Defines the base address of the ATCM. The base address must be aligned to the size of the ATCM. Any bits in the range [(log2(RAMSize)-1):12] are ignored.

At reset, if LOCZRAMA is set to:

0 = The initial base address is implementation-defined. See Configurable options

1 = The initial base address is 0x0.

Value: 0 [11:7] - UNP on reads, SBZ on writes.

Value: 14(0xE) [6:2] Size Size. Indicates the size of the ATCM on reads. On writes this field is ignored. See About the TCMs.

b00000 = 0KB

b00011 = 4KB

b00100 = 8KB

b00101 = 16KB

b00110 = 32KB

b00111 = 64KB

b01000 = 128KB

b01001 = 256KB

b01010 = 512kB

b01011 = 1MB

b01100 = 2MB

b01101 = 4MB

b01110 = 8MB.

Value: 0 [1] - SBZ

Value: 0 [0]

Enable

Enables or disables the ATCM.

0 = Disabled

1 = Enabled. The reset value of this field is determined by the INITRAMA input pin.

To access the ATCM Region Register, read or write CP15 with:

MRC p15, 0, , c9, c1, 1 ; Read ATCM Region Register

MCR p15, 0, , c9, c1, 1 ; Write ATCM Region Register

---------------------------

4.3.25. c11, Slave Port Control Register

The Slave Port Control Register characteristics are:

Purpose

Enables or disables TCM access to the AXI slave port in Privileged or User mode.

Enables access to the cache RAMs through the AXI slave port. See c1, Auxiliary Control Register.

Usage constraints

The Slave Port Control Register is:

a read/write register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.43.

Figure 4.42 shows the Slave Port Control Register bit assignments.

Figure 4.42. Slave Port Control Register bit assignments

Table 4.43 shows the Slave Port Control Register bit assignments.

Table 4.43. Slave Port Control Register bit assignments

Bits Name Function

Value: 0 [31:2] - RAZ/UNP

Value: 0 [1] Privileged access

Defines level of access for TCM accesses:

0 = Non-privileged and privileged access. This is the reset value.

1 = Privileged access only.

Value: 0 [0] AXI slave enable

Enables or disables the AXI slave port for TCM accesses:

0 = Enables AXI slave port. This is the reset value.

1 = Disables AXI slave port.

To access the Slave Port Control Register, read or write CP15 with:

MRC p15, 0, , c11, c0, 0 ; Read Slave Port Control Register

MCR p15, 0, , c11, c0, 0 ; Write Slave Port Control Register

-----------------------------------

4.3.27. c13, Context ID Register

The CONTEXTIDR characteristics are:

Purpose

Holds a process IDentification (ID) value for the running process.

The Embedded Trace Macrocell (ETM) and the debug logic use this register. The ETM can broadcast its value to indicate the process that is running. You must program each process with a unique number.

Enables process dependent breakpoints and instructions.

Usage constraints

The CONTEXTIDR is:

a read/write register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

The CONTEXTIDR, bits [31:0] contain the process ID number.

To use the CONTEXTIDR, read or write CP15 with:

MRC p15, 0, , c13, c0, 1 ; Read CONTEXTIDR

MCR p15, 0, , c13, c0, 1 ; Write CONTEXTIDR

----------------------------------

4.3.28. c13, Thread and Process ID Registers

The Thread and Process ID Registers provide locations to store the IDs of software threads and processes for Operating System (OS) management purposes.

The Thread and Process ID Registers are:

three read/write registers:

User read/write Thread and Process ID Register

User read-only Thread and Process ID Register

Privileged-only Thread and Process ID Register.

each accessible in different modes:

The User read/write register can be read and written in User and Privileged modes.

The User read-only register can only be read in User mode, but can be read and written in Privileged modes.

The Privileged-only register can be read and written in Privileged modes only.

To access the Thread and Process ID registers, read or write CP15 with:

MRC p15, 0, , c13, c0, 2 ; Read User read/write Thread and Proc. ID Register

MCR p15, 0, , c13, c0, 2 ; Write User read/write Thread and Proc. ID Register

MRC p15, 0, , c13, c0, 3 ; Read User Read Only Thread and Proc. ID Register

MCR p15, 0, , c13, c0, 3 ; Write User Read Only Thread and Proc. ID Register

MRC p15, 0, , c13, c0, 4 ; Read Privileged Only Thread and Proc. ID Register

MCR p15, 0, , c13, c0, 4 ; Write Privileged Only Thread and Proc. ID Register

Reading or writing the Thread and Process ID registers has no effect on processor state or operation. These registers provide OS support, and the OS must manage them.

You must clear the contents of all Thread and Process ID registers on process switches to prevent data leaking from one process to another. This is important to ensure the security of data. The reset value of these registers is 0.

--------------------------------

4.3.29. Validation Registers

The processor implements a set of validation registers. This section describes:

c15, nVAL IRQ Enable Set Register

c15, nVAL FIQ Enable Set Register

c15, nVAL Reset Enable Set Register

c15, VAL Debug Request Enable Set Register

c15, nVAL IRQ Enable Clear Register

c15, nVAL FIQ Enable Clear Register

c15, nVAL Reset Enable Clear Register

c15, VAL Debug Request Enable Clear Register

c15, Cache Size Override Register.

c15, nVAL IRQ Enable Set Register

The nVAL IRQ Enable Set Register characteristics are:

Purpose

Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, to generate an interrupt request on overflow. If enabled, the interrupt request is signaled by nVALIRQ being asserted LOW.

Usage constraints

The nVAL IRQ Enable Set Register is:

A read/write register.

Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

See Table 4.44.

Figure 4.43 shows the nVAL IRQ Enable Set Register bit assignments.

Figure 4.43. nVAL IRQ Enable Set Register bit assignments

Table 4.44 shows the nVAL IRQ Enable Set Register bit assignments.

Table 4.44. nVAL IRQ Enable Set Register bit assignments

Bits

Name Function

Value: 0 [31] C PMCCNTR overflow IRQ request

Value: 0 [30: 3] - UNP or SBZP

Value: 0 [2] P2 PMC2 overflow IRQ request

Value: 0 [1] P1 PMC1 overflow IRQ request

Value: 0 [0] P0 PMC0 overflow IRQ request

To access the nVAL IRQ Enable Set Register, read or write CP15 with:

MRC p15, 0, , c15, c1, 0 ; Read nVAL IRQ Enable Set Register

MCR p15, 0, , c15, c1, 0 ; Write nVAL IRQ Enable Set Register

On reads, this register returns the current setting. On writes, interrupt requests can be enabled by writing a 1 to the appropriate bits. If an interrupt request is enabled it is disabled by writing to the nVAL IRQ Enable Clear Register, see c15, nVAL IRQ Enable Clear Register.

If one or more of the IRQ request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then an IRQ request is indicated by nVALIRQ being asserted LOW. This signal might be passed to a system interrupt controller.

c15, nVAL FIQ Enable Set Register

The nVAL FIQ Enable Set Register characteristics are:

Purpose

Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, to generate an fast interrupt request on overflow. If enabled, the interrupt request is signaled by nVALFIQ being asserted LOW.

Usage constraints

The nVAL FIQ Enable Set Register is:

A read/write register.

Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

See Table 4.45.

Figure 4.44 shows the nVAL FIQ Enable Set Register bit assignments.

Figure 4.44. nVAL FIQ Enable Set Register bit assignments

Table 4.45 shows the nVAL FIQ Enable Set Register bit assignments.

Table 4.45. nVAL FIQ Enable Set Register bit assignments

Bits

Name Function

Value: 0 [31] C PMCCNTR overflow FIQ request

Value: 0 [30:3] - UNP or SBZP

Value: 0 [2] P2 PMC2 overflow FIQ request

Value: 0 [1] P1 PMC1 overflow FIQ request

Value: 0 [0] P0 PMC0 overflow FIQ request

To access the FIQ Enable Set Register, read or write CP15 with:

MRC p15, 0, , c15, c1, 1 ; Read FIQ Enable Set Register

MCR p15, 0, , c15, c1, 1 ; Write FIQ Enable Set Register

On reads, this register returns the current setting. On writes, interrupt requests can be enabled by writing a 1 to the appropriate bits. If an interrupt request is enabled it is disabled by writing to the FIQ Enable Clear Register, see c15, nVAL FIQ Enable Clear Register.

If one or more of the FIQ request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then an FIQ request is indicated by nVALFIQ being asserted LOW. This signal can be passed to a system interrupt controller.

c15, nVAL Reset Enable Set Register

The nVAL Reset Enable Set Register is:

A read/write register.

Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

The nVAL Reset Enable Set Register characteristics are:

Purpose

Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, to generate a reset request on overflow. If enabled, the reset request is signaled by nVALRESET being asserted LOW.

Usage constraints

The nVAL Reset Enable Set Register is:

A read/write register.

Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

See Table 4.46.

Figure 4.45 shows the nVAL Reset Enable Set Register bit assignments.

Figure 4.45. nVAL Reset Enable Set Register bit assignments

Table 4.46 shows the nVAL Reset Enable Set Register bit assignments.

Table 4.46. nVAL Reset Enable Set Register bit assignments

Bits

Name Function

Value: 0 [31] C PMCCNTR overflow reset request

Value: 0 [30:3] - UNP or SBZP

Value: 0 [2] P2 PMC2 overflow reset request

Value: 0 [1] P1 PMC1 overflow reset request

Value: 0 [0] P0 PMC0 overflow reset request

To access the nVAL Reset Enable Set Register, read or write CP15 with:

MRC p15, 0, , c15, c1, 2 ; Read nVAL Reset Enable Set Register

MCR p15, 0, , c15, c1, 2 ; Write nVAL Reset Enable Set Register

On reads, this register returns the current setting. On writes, interrupt requests can be enabled by writing a 1 to the appropriate bits. If a reset request is enabled, it is disabled by writing to the nVAL Reset Enable Clear Register. See c15, nVAL Reset Enable Clear Register.

If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then a reset request is indicated by nVALRESET being asserted LOW. This signal can be passed to a system reset controller.

c15, VAL Debug Request Enable Set Register

The VAL Debug Request Enable Set Register characteristics are:

Purpose

Enables any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, to generate a debug request on overflow. If enabled, the debug request is signaled by VALEDBGRQ being asserted HIGH.

Usage constraints

The VAL Debug Request Enable Set Register is:

A read/write register.

Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

See Table 4.47.

Figure 4.46 shows the VAL Debug Request Enable Set Register bit assignments.

Figure 4.46. VAL Debug Request Enable Set Register bit assignments

Table 4.47 shows the VAL Debug Request Enable Set Register bit assignments.

Table 4.47. VAL Debug Request Enable Set Register bit assignments

Bits

Name Function

Value: 0 [31] C PMCCNTR overflow debug request

Value: 0 [30:3] - UNP or SBZP

Value: 0 [2] P2 PMC2 overflow debug request

Value: 0 [1] P1 PMC1 overflow debug request

Value: 0 [0] P0 PMC0 overflow debug request

To access the nVAL Debug Request Enable Set Register, read or write CP15 with:

MRC p15, 0, , c15, c1, 3 ; Read nVAL Debug Request Enable Set Register

MCR p15, 0, , c15, c1, 3 ; Write nVAL Debug Request Enable Set Register

On reads, this register returns the current setting. On writes, interrupt requests can be enabled by writing a 1 to the appropriate bits. If a debug request is enabled, it is disabled by writing to the nVAL Debug Request Enable Clear Register. See c15, VAL Debug Request Enable Clear Register.

If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then a debug reset request is indicated by VALEDBGRQ being asserted HIGH. This signal can be passed to an external debugger.

c15, nVAL IRQ Enable Clear Register

The nVAL IRQ Enable Clear Register characteristics are:

Purpose

Disables overflow IRQ requests from any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, for which they have been enabled.

Usage constraints

The nVAL IRQ Enable Clear Register is:

A read/write register.

Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

See Table 4.48.

Figure 4.47 shows the nVAL IRQ Enable Clear Register bit assignments.

Figure 4.47. nVAL IRQ Enable Clear Register bit assignments

Table 4.48 shows the nVAL IRQ Enable Clear Register bit assignments.

Table 4.48. nVAL IRQ Enable Clear Register bit assignments

Bits

Name Function

Value: 0 [31] C PMCCNTR overflow IRQ request

Value: 0 [30:3] - UNP or SBZP

Value: 0 [2] P2 PMC2 overflow IRQ request

Value: 0 [1] P1 PMC1 overflow IRQ request

Value: 0 [0] P0 PMC0 overflow IRQ request

To access the nVAL IRQ Enable Clear Register, read or write CP15 with:

MRC p15, 0, , c15, c1, 4 ; Read nVAL IRQ Enable Clear Register

MCR p15, 0, , c15, c1, 4 ; Write nVAL IRQ Enable Clear Register

On reads, this register returns the current setting. On writes, overflow interrupt requests that are enabled can be disabled by writing a 1 to the appropriate bits.

For more information of how to enable IRQ requests on counter overflows, and how the requests are signaled, see c15, nVAL IRQ Enable Set Register.

c15, nVAL FIQ Enable Clear Register

The nVAL FIQ Enable Clear Register characteristics are:

Purpose

Disables overflow FIQ requests from any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, that are enabled.

Usage constraints

The nVAL FIQ Enable Clear Register is:

A read/write register.

Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

See Table 4.49.

Figure 4.48 shows the nVAL FIQ Enable Clear Register bit assignments.

Figure 4.48. nVAL FIQ Enable Clear Register bit assignments

Table 4.49 shows the nVAL FIQ Enable Clear Register bit assignments.

Table 4.49. nVAL FIQ Enable Clear Register bit assignments

Bits

Name Function

Value: 0 [31] C PMCCNTR overflow FIQ request

Value: 0 [30:3] - UNP or SBZP

Value: 0 [2] P2 PMC2 overflow FIQ request

Value: 0 [1] P1 PMC1 overflow FIQ request

Value: 0 [0] P0 PMC0 overflow FIQ request

To access the FIQ Enable Clear Register, read or write CP15 with:

MRC p15, 0, , c15, c1, 5 ; Read FIQ Enable Clear Register

MCR p15, 0, , c15, c1, 5 ; Write FIQ Enable Clear Register

On reads, this register returns the current setting. On writes, overflow interrupt requests that are enabled can be disabled by writing a 1 to the appropriate bits.

For information on how to enable FIQ requests on counter overflows, and how the requests are signaled, see c15, nVAL FIQ Enable Set Register.

c15, nVAL Reset Enable Clear Register

The nVAL Reset Enable Clear Register characteristics are:

Purpose

Disables overflow reset requests from any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, that are enabled.

Usage constraints

The nVAL Reset Enable Clear Register is:

A read/write register.

Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

See Table 4.50.

Figure 4.49 shows the nVAL Reset Enable Clear Register bit assignments.

Figure 4.49. nVAL Reset Enable Clear Register bit assignments

Table 4.50 shows the nVAL Reset Enable Clear Register bit assignments.

Table 4.50. nVAL Reset Enable Clear Register bit assignments

Bits

Name Function

Value: 0 [31] C PMCCNTR overflow reset request

Value: 0 [30:3] - UNP or SBZP

Value: 0 [2] P2 PMC2 overflow reset request

Value: 0 [1] P1 PMC1 overflow reset request

Value: 0 [0] P0 PMC0 overflow reset request

To access the nVAL Reset Enable Clear Register, read or write CP15 with:

MRC p15, 0, , c15, c1, 6 ; Read nVAL Reset Enable Clear Register

MCR p15, 0, , c15, c1, 6 ; Write nVAL Reset Enable Clear Register

On reads, this register returns the current setting. On writes, overflow reset requests that are enabled can be disabled by writing a 1 to the appropriate bits.

For more information of how to enable reset requests on counter overflows, and how the requests are signaled, see c15, nVAL Reset Enable Set Register.

c15, VAL Debug Request Enable Clear Register

The VAL Debug Request Enable Clear Register characteristics are:

Purpose

Disables overflow debug requests from any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2, and PMCCNTR, that are enabled.

Usage constraints

The VAL Debug Request Enable Clear Register is:

A read/write register.

Always accessible in Privileged mode. The PMUSERENR Register determines access in User mode, see c9, User Enable Register.

Configurations

Available in all processor configurations.

Attributes

See Table 4.51.

Figure 4.50 shows the VAL Debug Request Enable Clear Register bit assignments.

Figure 4.50. VAL Debug Request Enable Clear Register bit assignments

Table 4.51 shows the VAL Debug Request Enable Clear Register bit assignments.

Table 4.51. VAL Debug Request Enable Clear Register bit assignments

Bits

Name Function

Value: 0 [31] C PMCCNTR overflow debug request

Value: 0 [30:3] - UNP or SBZP

Value: 0 [2] P2 PMC2 overflow debug request

Value: 0 [1] P1 PMC1 overflow debug request

Value: 0 [0] P0 PMC0 overflow debug request

To access the nVAL Debug Request Enable Clear Register, read or write CP15 with:

MRC p15, 0, , c15, c1, 7 ; Read nVAL Debug Request Enable Clear Register

MCR p15, 0, , c15, c1, 7 ; Write nVAL Debug Request Enable Clear Register

On reads, this register returns the current setting. On writes, overflow debug requests that are enabled can be disabled by writing a 1 to the appropriate bits.

For more information of how to enable debug requests on counter overflows, and how the requests are signaled, see c15, VAL Debug Request Enable Set Register.

c15, Cache Size Override Register

The Cache Size Override Register characteristics are:

Purpose

Overwrites the caches size fields in the main register. This enables you to choose a smaller instruction and data cache size than is implemented.

Usage constraints

The Cache Size Override Register is:

a write-only register

only accessible in Privileged mode.

Configurations

Available in all processor configurations.

Attributes

See Table 4.52.

Figure 4.51 shows the Cache Size Override Register bit assignments.

Figure 4.51. Cache Size Override Register bit assignments

Table 4.52 shows the Cache Size Override Register bit assignments.

Table 4.52. Cache Size Override Register bit assignments

Bits

Name Function

Value: 0 [31:8] - SBZ.

Value: 0 [7:4] Dcache

Defines the data cache size override value. See Table 4.53.

Value: 0 [3:0] Icache

Defines the instruction cache size override value. See Table 4.53.

Table 4.53 shows the encodings for the instruction and data cache sizes.

Table 4.53. instruction and data cache size encodings

Encoding Instruction and data cache size

b0000 4kB

b0001 8kB

b0011 16kB

b0111 32kB

b1111 64kB

To access the Cache Size Override Register, write CP15 with:

MCR p15, 0, , c15, c14, 0 ; VAL Cache Size Override Register

Note

The Cache Size Override Register can only be used to select cache sizes for which the appropriate RAM is integrated. Larger cache sizes require deeper data and tag RAMs, and smaller cache sizes require wider tag RAMs. Therefore, it is unlikely that you can change the cache size using this register except using a simulation model of the cache RAMs.

------------------------------

4.3.30. Correctable Fault Location Register

The CFLR characteristics are:

Purpose

Indicates the location of the last correctable error that occurred during cache or TCM operations.

Usage constraints

The CFLR is:

a read/write register

accessible in Privileged mode only

not updated on:

speculative accesses, for example, an instruction fetch for an instruction that is not executed because of a previous branch

a TCM external error or external retry request.

updated on:

parity or ECC errors in the instruction cache

single-bit ECC errors in the data cache

parity or multi-bit errors in the data cache when write-through behavior is forced

single-bit TCM ECC errors.

updated by the processor, regardless of whether an abort is taken or an access is retried in response to the error.

Configurations

Available in all processor configurations.

Attributes

See Table 4.54.

Every correctable error that causes a CFLR update also has an associated event. See Table 6.1 for the events that are related to CFLR updates. If two correctable errors occur simultaneously, for example an AXI slave error and an LSU or PFU error, the LSU or PFU write takes priority. If multiple errors occur, the value in the CFLR reflects the location of the latest event.

The same register is updated by all correctable errors. You can read bits [25:24] to determine whether the error was from a cache or TCM access.

Figure 4.52 shows the CFLR bit assignments, when it indicates a correctable cache error.

Figure 4.52. CFLR - cache, bit assignments

Table 4.54 shows the CFLR bit assignments, when it indicates a correctable cache error.

Table 4.54. CFLR - cache, bit assignments

Bits Name Function

Value: 0 [31:30] - RAZ

Value: 0 [29:26] Way Indicates the Way of the error.

Value: 0 [25:24] Side Indicates the source of the error. For cache errors, this value is always 0b00.

Value: 0 [23:14] - RAZ

Value: 0 [13:5] Index Indicates the index of the location where the error occurred.

Value: 0 [4:2] - RAZ

Value: 0 [1:0] Type

Indicates the type of access that caused the error:

0b00 = Instruction cache.

0b01 = Data cache.

Figure 4.53 shows the CFLR bit assignments, when it indicates a correctable TCM error.

Figure 4.53. CFLR - TCM, bit assignments

Table 4.55 shows the CFLR bit assignments, when it indicates a correctable TCM error.

Table 4.55. CFLR - TCM, bit assignments

Bits Name Function

Value: 0 [31:26] - RAZ

Value: 0 [25:24] Side

Indicates the source of the error:

0b01 = ATCM

0b10 = BTCM

Value: 0 [23] - RAZ

Value: 0 [22:3] Address Indicates the address in the TCM where the error occurred.

Value: 0 [2] - RAZ

Value: 0 [1:0] Type

Indicates the type of access that caused the error:

0b00 = Instruction.

0b01 = Data.

0b10 = AXI slave

0b11 is unused.

To access the CFLR, read or write CP15 with:

MRC p15, 0, , c15, c3, 0 : Read CFLR

MCR p15, 0, , c15, c3, 0 : Write CFLR

--------------------------------

4.3.31. Build Options Registers

Note

These registers are implemented from the r1pn releases of the processor. Attempting to access these registers in r0pn releases of the processor results in an Undefined Instruction exception.

c15, Build Options 1 Register

The Build Options 1 Register characteristics are:

Purpose

Reflects the build configuration options used to build the processor.

Usage constraints

The Build Options 1 Register is:

a read-only register

accessible in Privileged mode only

Configurations

Available in all processor configurations.

Attributes

See Table 4.56.

Figure 4.54 shows the Build Options 1 Register bit assignments.

Figure 4.54. Build Options 1 Register bit assignments

Table 4.56 shows the Build Options 1 Register bit assignments.

Table 4.56. Build Options 1 Register bit assignments

Bits Name Function

Value: 2048(0x800) [31:12] TCM_HI_INIT_ADDR Default high address for the TCM.

Value: 0 [11:0] - SBZ

To access the Build Options 1 Register, read CP15 with:

MRC p15, 0, , c15, c2, 0 ; read Build Options 1 Register

c15, Build Options 2 Register

The Build Options 2 Register characteristics are:

Purpose

Reflects the build configuration options used to build the processor.

Usage constraints

The Build Options 2 Register is:

a read-only register

accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 4.57.

Figure 4.55 shows the Build Options 2 Register bit assignments.

Figure 4.55. Build Options 2 Register bit assignments

Table 4.57 shows the Build Options 2 Register bit assignments.

Table 4.57. Build Options 2 Register bit assignments

Bits Name Function

Value: 0 [31] DUAL_CORE[a]

Indicates whether a second, redundant, copy of the processor logic and checking logic was instantiated:

0 = single core

1 = dual core.

Value: 0 [30] DUAL_NCLK[a]

Indicates whether an inverted clock is used for the redundant core:

0 = inverted clock not used

1 = inverted clock used.

Value: 0 [29] NO_ICACHE

Indicates whether the processor contains instruction cache:

0 = processor contains instruction cache

1 = processor does not contain instruction cache.

Value: 0 [28] NO_DCACHE

Indicates whether the processor contains data cache:

0 = processor contains data cache

1 = processor does not contain data cache.

Value: 0 [27:26] ATCM_ES

Indicates whether an error scheme is implemented on the ATCM interface:

00 = no error scheme

01 = 8-bit parity logic

10 = 32-bit error detection and correction

11 = 64-bit error detection and correction.

Value: 0 [25:24] BTCM_ES

Indicates whether an error scheme is implemented on the BTCM interface(s):

00 = no error scheme

01 = 8-bit parity logic

10 = 32-bit error detection and correction

11 = 64-bit error detection and correction.

Value: 0 [23] NO_IE

Indicates whether the processor supports big-endian instructions:

0 = processor supports big-endian instructions

1 = processor does not support big-endian instructions.

Value: 0 [22] NO_FPU

Indicates whether the processor contains a floating point unit:

0 = processor contains a floating point unit

1 = processor does not contain a floating point unit.

Value: 0 [21] NO_MPU

Indicates whether the processor contains a Memory Protection Unit (MPU):

0 = processor contains an MPU

1 = processor does not contain an MPU.

Value: 0 [20] MPU_REGIONS

Indicates the number of regions in the included MPU:

0 = 8

1 = 12.

If the processor does not contain an MPU (bit [21] set to 0), this bit is set to 0.

Value: 3 [19:17] BREAK_POINTS

Indicates the number of break points implemented in the processor, minus 1.

Value: 3 [16:14] WATCH_POINTS

Indicates the number of watch points implemented in the processor, minus 1.

Value: 0 [13] NO_A_TCM_INF

Indicates whether the processor contains an ATCM port:

0 = processor contains ATCM port

1 = processor does not contain ATCM port.

Value: 0 [12] NO_B0_TCM_INF

Indicates whether the processor contains a B0TCM port:

0 = processor contains B0TCM port

1 = processor does not contain B0TCM port.

Value: 0 [11] NO_B1_TCM_INF

Indicates whether the processor contains a B1TCM port:

0 = processor contains B1TCM port

1 = processor does not contain B1TCM port.

Value: 0 [10] TCMBUSPARITY

Indicates whether the processor contains TCM address bus parity logic:

0 = processor does not contain TCM address bus parity logic

1 = processor contains TCM address bus parity logic.

Value: 0 [9] NO_SLAVE

Indicates whether the processor contains an AXI slave port:

0 = processor contains an AXI slave port

1 = processor does not contain an AXI slave port.

Value: 0 [8:7] ICACHE_ES

Indicates whether an error scheme is implemented for the instruction cache:

00 = no error scheme

01 = 8-bit parity error detection

11 = 64-bit error detection and correction.

If the processor does not contain an Icache, these bits are set to 00.

Value: 0 [6:5] DCACHE_ES

Indicates whether an error scheme is implemented for the data cache:

00 = no error scheme

01 = 8-bit parity error detection

10 = 32-bit error detection and correction.

If the processor does not contain a Dcache, these bits are set to0b00.

Value: 0 [4] NO_HARD_ERROR_CACHE

Indicates whether the processor contains cache for corrected TCM errors:

0 = processor contains TCM error cache

1 = processor does not contain TCM error cache.

Value: 0 [3] AXIBUSPARITY

Indicates whether the processor contains AXI bus parity logic.

0 = processor does not contain AXI bus parity logic

1 = processor contains AXI bus parity logic.

Value: 0 [2:0] - Undefined.

[a] The value of this bit is Unpredictable in revision r1p0 of the processor.

To access the Build Options 2 Register, write CP15 with:

MRC p15, 0, , c15, c2, 1 ; read Build Options 2 Register

Table 4.23. SCTLR Register bit assignments

Bits

Name

Function

Value: 0 [31]

Identifies little or big instruction endianness in use:

0 = little-endianness

1 = big-endianness.

The primary input CFGIE defines the reset value. This bit is read-only.

Value: 0 [30] TE

Thumb exception enable:

0 = enable ARM exception generation

1 = enable Thumb exception generation.

The primary input TEINIT defines the reset value.

Value: 0 [29] AFE Access Flag Enable. On the processor this bit is SBZ.

Value: 0 [28] TRE TEX Remap Enable. On the processor this bit is SBZ.

Value: 0 [27]

NMFI

NMFI, non-maskable fast interrupt enable:

0 = Software can disable FIQs

1 = Software cannot disable FIQs.

This bit is read-only. The configuration input CFGNMFI defines its value.

Value: 0 [26] - SBZ.

Value: 0 [25] EE

Determines how the E bit in the CPSR is set on an exception:

0 = CPSR E bit is set to 0 on an exception

1 = CPSR E bit is set to 1 on an exception.

The primary input CFGEE defines the reset value.

Value: 0 [24] VE

Configures vectored interrupt:

0 = exception vector address for IRQ is 0x00000018 or 0xFFFF0018. See V bit.

1 = VIC controller provides handler address for IRQ.

The reset value of this bit is 0.

Value: 1 [23:22] -

SBO.

Value: 0 [21] FI

Fast Interrupts enable.

On the processor Fast Interrupts are always enabled. This bit is SBO.

Value: 0 [20] - SBZ.

Value: 0 [19] DZ

Divide by zero:

0 = do not generate an Undefined Instruction exception

1 = generate an Undefined Instruction exception.

The reset value of this bit is 0.

Value: 0 [18] - SBO.

Value: 0 [17] BR MPU background region enable.

Value: 0 [16] - SBO.

Value: 0 [15] - SBZ.

Value: 0 [14] RR

Round-robin bit, controls replacement strategy for instruction and data caches:

0 = random replacement strategy

1 = round-robin replacement strategy.

The reset value of this bit is 0. The processor always uses a random replacement strategy, regardless of the state of this bit.

Value: 0 [13]

Determines the location of exception vectors:

0 = normal exception vectors selected, address range = 0x00000000-0x0000001C

1 = high exception vectors (HIVECS) selected, address range = 0xFFFF0000-0xFFFF001C.

The primary input VINITHI defines the reset value.

Value: 0 [12]

Enables L1 instruction cache:

0 = instruction caching disabled. This is the reset value.

1 = instruction caching enabled.

If no instruction cache is implemented, then this bit is SBZ.

Value: 0 [11] Z

Branch prediction enable bit.

The processor supports branch prediction. This bit is SBO. The ACTLR can control branch prediction, see c1, Auxiliary Control Register.

Value: 0 [10:7] - SBZ.

Value: 7 [6:3] - SBO.

Value: 0 [2]

Enables L1 data cache:

0 = data caching disabled. This is the reset value.

1 = data caching enabled.

If no data cache is implemented, then this bit is SBZ.

Value: 0 [1]

Enables strict alignment of data to detect alignment faults in data accesses:

0 = strict alignment fault checking disabled. This is the reset value.

1 = strict alignment fault checking enabled.

Value: 0 [0]

Enables the MPU:

0 = MPU disabled. This is the reset value.

1 = MPU enabled.

If no MPU is implemented, this bit is SBZ.

To use the SCTLR, ARM recommends that you use a read-modify-write technique. To access the SCTLR, read or write CP15 with:

MRC p15, 0, , c1, c0, 0 ; Read SCTLR

MCR p15, 0, , c1, c0, 0 ; Write SCTLR

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